Modeling of a Hump Effect Using a Three-Dimensional TCAD Device Simulator

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F19%3A00340359" target="_blank" >RIV/68407700:21230/19:00340359 - isvavai.cz</a>
Result on the web
<a href="http://poseidon2.feld.cvut.cz/conf/poster/" target="_blank" >http://poseidon2.feld.cvut.cz/conf/poster/</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Modeling of a Hump Effect Using a Three-Dimensional TCAD Device Simulator
Original language description
In this paper, we have analyzed the hump effect of polysilicon planar NMOS transistors. The hump effect caused by boron segregation makes a negative effect on transfer characteristic in the sub-threshold region of high voltage transistors. Therefore, we have analyzed the hump effect for several geometries, where various physical parameters have been lengths of MOS transistors, and gate thicknesses oxide of MOS transistors. Moreover, it has been studied for different simulation parameter. As the simulation parameters have been various gate-source voltages VGS, and bulk-source voltage VBS. In order to respect the hump effect in circuit level simulations, there has been verified a macromodel of the MOS transistor with the hump effect. All simulations have been run by the 3D TCAD Silvaco simulation tool.
Czech name
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Czech description
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Publication year
2019
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the International Student Scientific Conference Poster – 23/2019
ISBN
978-80-01-06581-5
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
61-64
Publisher name
ČVUT FEL, Středisko vědecko-technických informací
Place of publication
Praha
Event location
ČVUT FEL, Technická 2, Praha 6
Event date
May 23, 2019
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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