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MOSFETs’ Electrical Performance in the 160-nm BCD Technology Process With the Diamond Layout Shape

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F20%3A00342237" target="_blank" >RIV/68407700:21230/20:00342237 - isvavai.cz</a>

  • Result on the web

    <a href="https://doi.org/10.1109/TED.2020.3000744" target="_blank" >https://doi.org/10.1109/TED.2020.3000744</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/TED.2020.3000744" target="_blank" >10.1109/TED.2020.3000744</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    MOSFETs’ Electrical Performance in the 160-nm BCD Technology Process With the Diamond Layout Shape

  • Original language description

    This article introduces an innovative approach that describes the drain–source current improvements of MOS transistors. It is based on the geometrical modification of MOSFET’s channel from a rectangular layout shape (RLS) into a diamond layout shape (DLS). In this way, the drain–source current enhancement is increased up to 11% for the DLS MOS transistors with an effective aspect ratio (W/L)eff equal to 2.0 and an angle set to 80. Moreover, we present the comparison of 3-D TCAD simulations data, analytical model data based on Schwarz–Christoffel transformation (SCT), and measurement data given by the measurement of the MOS transistors fabricated in the Bipolar- CMOS-DMOS (BCD) 160-nm technology process. For this purpose, there have been fabricated 1124 samples, which were proportionally divided into RLS MOSFETs and DLS MOSFETs with the angles equal to 120, 100, and 80. For all studied aspect ratios, the presented model has an excellent analytic description in comparison with the 3-D TCAD simulation results with an error lower than 3%. So, it proves the quality of the analytical model based on the SCT approach and it is the recommended approach to use also for modeling other MOSFET gate layout shapes.

  • Czech name

  • Czech description

Classification

  • Type

    J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database

  • CEP classification

  • OECD FORD branch

    20201 - Electrical and electronic engineering

Result continuities

  • Project

  • Continuities

    S - Specificky vyzkum na vysokych skolach

Others

  • Publication year

    2020

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Name of the periodical

    IEEE Transactions on Electron Devices

  • ISSN

    0018-9383

  • e-ISSN

    1557-9646

  • Volume of the periodical

    67

  • Issue of the periodical within the volume

    8

  • Country of publishing house

    US - UNITED STATES

  • Number of pages

    8

  • Pages from-to

    3270-3277

  • UT code for WoS article

    000552976100040

  • EID of the result in the Scopus database

    2-s2.0-85089354475