Techniques for SAT-Based Constrained Test Pattern Generation
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F11%3A00182466" target="_blank" >RIV/68407700:21240/11:00182466 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/DSD.2011.50" target="_blank" >http://dx.doi.org/10.1109/DSD.2011.50</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2011.50" target="_blank" >10.1109/DSD.2011.50</a>
Alternative languages
Result language
angličtina
Original language name
Techniques for SAT-Based Constrained Test Pattern Generation
Original language description
Testing of digital circuits seems to be a completely mastered part of the design flow, but constrained test patterns generation is still a highly evolving branch of digital circuit testing. Our previous research on constrained test pattern generation proved that we can benefit from an implicit representation of test patterns set in CNF (Conjunctive Normal Form). Some techniques of speeding up the constrained SATbased test patterns generation are described and closely analyzed in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a constrained test patterns compression based on overlapping of test patterns. Experiments are performed on a subset of ISCAS'85 and '89 benchmark circuits. Results of the experiments are discussed and recommendations for a further development of similar SAT-based tools for constrained test patterns generation are given.
Czech name
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Czech description
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Classification
Type
D - Article in proceedings
CEP classification
JC - Computer hardware and software
OECD FORD branch
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Result continuities
Project
<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>
Continuities
Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach
Others
Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
Proceedings of the 14th Euromicro Conference on Digital System Design
ISBN
978-0-7695-4494-6
ISSN
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e-ISSN
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Number of pages
7
Pages from-to
360-366
Publisher name
IEEE Computer Society Press
Place of publication
Los Alamitos
Event location
Oulu
Event date
Aug 31, 2011
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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