Techniques for SAT-Based Constrained Test Pattern Generation

Result code in IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F13%3A00203004" target="_blank" >RIV/68407700:21240/13:00203004 - isvavai.cz</a>

Result on the web

<a href="http://dx.doi.org/10.1016/j.micpro.2012.09.010" target="_blank" >http://dx.doi.org/10.1016/j.micpro.2012.09.010</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1016/j.micpro.2012.09.010" target="_blank" >10.1016/j.micpro.2012.09.010</a>

Result language

angličtina

Original language name

Techniques for SAT-Based Constrained Test Pattern Generation

Original language description

Testing of digital circuits seems to be a completely mastered part of the design flow, but Constrained Test Patterns Generation (CTPG) is still a highly evolving branch of digital circuits testing. Our previous research on CTPG proved that we can benefitfrom an implicit representation of test patterns set. The set of test patterns is implicitly represented as a Boolean formula satisfiability problem in CNF, like in common SAT-based ATPGs. However, the CTPG process can be much more memory or time consuming than common TPG, thus some techniques of speeding up the constrained SAT-based test patterns generation are described and analyzed into detail in this paper. These techniques are experimentally evaluated on a real SAT-based algorithm performing a test compression based on overlapping of test patterns. Experiments are performed on ISCAS?85, ?89 and ITC?99 benchmark circuits. Results of the experiments are discussed and recommendations for further development of similar SAT-based tools

Czech name

—

Czech description

—

Type

J_x - Unclassified - Peer-reviewed scientific article (Jimp, Jsc and Jost)

CEP classification

JC - Computer hardware and software

OECD FORD branch

—

Project

<a href="/en/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: SoC circuits reliability and availability improvement</a><br>

Continuities

Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Publication year

2013

Confidentiality

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Name of the periodical

Microprocessors and Microsystems

ISSN

0141-9331

e-ISSN

—

Volume of the periodical

37

Issue of the periodical within the volume

2

Country of publishing house

NL - THE KINGDOM OF THE NETHERLANDS

Number of pages

11

Pages from-to

185-195

UT code for WoS article

000317166000007

EID of the result in the Scopus database

—