An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F14%3A00224305" target="_blank" >RIV/68407700:21240/14:00224305 - isvavai.cz</a>
Result on the web
<a href="http://dx.doi.org/10.1109/ICECS.2014.7050083" target="_blank" >http://dx.doi.org/10.1109/ICECS.2014.7050083</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/ICECS.2014.7050083" target="_blank" >10.1109/ICECS.2014.7050083</a>

Result language
angličtina
Original language name
An ASIC Linear Congruence Solver Synthesized with Three Cell Libraries
Original language description
The paper describes an ASIC implementation of a linear congruence solver, part of a parallel system for solution of linear equations, and presents synthesis results for three different standard cell libraries. The previous VHDL design was adapted to three ASIC technologies (130 nm, 110 nm, and 55 nm) from two different vendors and the synthesized results were mutually compared. The comparison results were further used to obtain a view of design properties in higher density technologies.
Czech name
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Czech description
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Project
<a href="/en/project/GAP103%2F12%2F2377" target="_blank" >GAP103/12/2377: Study of properties of residual arithmetic for solving sets of linear equations</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2014
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 21st IEEE International Conference on Electronics Circuits and Systems
ISBN
978-1-4799-4242-8
ISSN
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e-ISSN
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Number of pages
4
Pages from-to
706-709
Publisher name
IEEE Circuits and Systems Society
Place of publication
Monterey
Event location
Marseille
Event date
Dec 7, 2014
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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