A Prudent Approach to Benchmark Collection

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F16%3A00301780" target="_blank" >RIV/68407700:21240/16:00301780 - isvavai.cz</a>
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
A Prudent Approach to Benchmark Collection
Original language description
We present experimental evidence that logic synthesis procedure, especially those based on resynthesis, do net perform well when the original (designer-given) structure of input description is lost. As such performance has not been observed otherwise, we must conclude that such operation is outside of the intended range, and that synthesis examples with their original structure lost are not valid for evaluation of synthesis procedures. We also outline other causes that may render an example invalid. We, however, document that such losses did occur with circuit examples circulating in the logic synthesis community. Therefore, we have to suggest what constitutes prudence in examples collection.
Czech name
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Czech description
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Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2016
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 12th International Workshop on Boolean Problems
ISBN
978-3-86012-540-3
ISSN
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e-ISSN
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Number of pages
8
Pages from-to
129-136
Publisher name
Freiberg University of Mining and Technology, Institute of Computer Science
Place of publication
Freiberg
Event location
Freiberg
Event date
Sep 22, 2016
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
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