A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00319199" target="_blank" >RIV/68407700:21240/18:00319199 - isvavai.cz</a>
Result on the web
<a href="https://www.cambridgescholars.com/further-improvements-in-the-boolean-domain" target="_blank" >https://www.cambridgescholars.com/further-improvements-in-the-boolean-domain</a>
DOI - Digital Object Identifier
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Result language
angličtina
Original language name
A Prudent Approach to Collection of Examples for Logic Synthesis and Optimization
Original language description
We present experimental evidence that logic synthesis procedure, especially those based on resynthesis, do net perform well when the original (designer-given) structure of input description is lost. As such performance has not been observed otherwise, we must conclude that such operation is outside of the intended range, and that synthesis examples with their original structure lost are not valid for evaluation of synthesis procedures. We also outline other causes that may render an example invalid. We, however, document that such losses did occur with circuit examples circulating in the logic synthesis community. Therefore, we have to suggest what constitutes prudence in examples collection.
Czech name
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Czech description
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Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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