SAT-based ATPG for Zero-Aliasing Compaction

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F17%3A00312889" target="_blank" >RIV/68407700:21240/17:00312889 - isvavai.cz</a>
Result on the web
<a href="http://ieeexplore.ieee.org/abstract/document/8049802/" target="_blank" >http://ieeexplore.ieee.org/abstract/document/8049802/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2017.73" target="_blank" >10.1109/DSD.2017.73</a>

Result language
angličtina
Original language name
SAT-based ATPG for Zero-Aliasing Compaction
Original language description
Aliasing in the test response compaction is an important source of fault coverage loss. Methods to combat the aliasing generally require modification of the compactor to some extent. This can lead to a higher compactor complexity and consequently to higher area overhead, longer signal propagation delays, etc. We propose a novel method, the Zero-aliasing ATPG (ZATPG), which is able to reduce the aliasing without need of designing new compactors. ZATPG works by augmenting the SAT-based ATPG process to constrain test pattern generation to produce no aliasing in the compactor. The method is general enough to be applicable to any compactor design. We demonstrate our method on LFSR-based MISR compactors, using the Single Stuck-At fault model. Our method is able to find a test with zero-aliasing and complete fault coverage for smaller compactors than conventional, unguided ATPG. Thus, the area overhead of the compactor can be reduced, while the complete fault coverage is retained.
Czech name
—
Czech description
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Project
<a href="/en/project/GA16-05179S" target="_blank" >GA16-05179S: Fault-Tolerant and Attack-Resistant Architectures Based on Programmable Devices: Research of Interplay and Common Features</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2017
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proc. of the 20th Euromicro Conference on Digital System Design
ISBN
978-1-5386-2146-2
ISSN
—
e-ISSN
—
Number of pages
8
Pages from-to
307-314
Publisher name
IEEE
Place of publication
Piscataway, NJ
Event location
Vienna
Event date
Aug 30, 2017
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000427097100043

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