Clock Domain Crossing – An Advanced Course for Future Digital Design Engineers
The result's identifiers
Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F18%3A00321846" target="_blank" >RIV/68407700:21240/18:00321846 - isvavai.cz</a>
Result on the web
<a href="https://ieeexplore.ieee.org/document/8406004/" target="_blank" >https://ieeexplore.ieee.org/document/8406004/</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/MECO.2018.8406004" target="_blank" >10.1109/MECO.2018.8406004</a>
Alternative languages
Result language
angličtina
Original language name
Clock Domain Crossing – An Advanced Course for Future Digital Design Engineers
Original language description
This paper describes the problem of crossing digital signals in a multi-clock digital designs in an ASIC/FPGA devices and the practical course focused on advanced FPGA design techniques and debugging for masters students of the study branch "Design and Programming of Embedded Systems". The course required to design a new printed circuit board to support course specific needs.
Czech name
—
Czech description
—
Classification
Type
D - Article in proceedings
CEP classification
—
OECD FORD branch
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Result continuities
Project
—
Continuities
S - Specificky vyzkum na vysokych skolach
Others
Publication year
2018
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Data specific for result type
Article name in the collection
2018 7th Mediterranean Conference on Embedded Computing (MECO)
ISBN
978-1-5386-5683-9
ISSN
—
e-ISSN
—
Number of pages
5
Pages from-to
76-80
Publisher name
IEEE
Place of publication
Piscataway
Event location
Budva
Event date
Jun 10, 2018
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
—