Standard Cell Tuning Enables Data-Independent Static Power Consumption

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F20%3A00341321" target="_blank" >RIV/68407700:21240/20:00341321 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1109/DDECS50862.2020.9095656" target="_blank" >https://doi.org/10.1109/DDECS50862.2020.9095656</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DDECS50862.2020.9095656" target="_blank" >10.1109/DDECS50862.2020.9095656</a>

Result language
angličtina
Original language name
Standard Cell Tuning Enables Data-Independent Static Power Consumption
Original language description
Physical attacks, namely invasive, observation and combined, represent a great challenge for today’s digital design. Successful class of strategies adopted by industry, allowing hiding data dependency of the side channel emissions in CMOS is based on balancing. Although attacks on CMOS dynamic power represent a class of state-of-the-art attacks, vulnerabilities exploiting data dependency in CMOS static power and light- modulated static power were recently presented. In this paper, we describe structures and techniques developed to enhance and balance traditional static CMOS bulk structures. To enable data dependency hiding, we propose low-level techniques based on complementary-value induced balancing currents, constant current source behavioral approximation, and light-sensing capability of traditional CMOS structures. The proposed techniques may be used to build a dual-rail circuit balanced from both perspectives: static and dynamic power. The publicly available TSMC180nm node standard cell simulation is used for evaluation.
Czech name
—
Czech description
—

Project
<a href="/en/project/EF16_019%2F0000765" target="_blank" >EF16_019/0000765: Research Center for Informatics</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Publication year
2020
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Article name in the collection
Proceedings of the 23rd International Symposium on Design and Diagnostics of Electronic Circuits and Systems
ISBN
978-1-7281-9938-2
ISSN
2334-3133
e-ISSN
—
Number of pages
6
Pages from-to
—
Publisher name
IEEE
Place of publication
Piscataway, NJ
Event location
Novi Sad
Event date
Apr 22, 2020
Type of event by nationality
WRD - Celosvětová akce
UT code for WoS article
000587761500013

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