All

What are you looking for?

All
Projects
Results
Organizations

Quick search

  • Projects supported by TA ČR
  • Excellent projects
  • Projects with the highest public support
  • Current projects

Smart search

  • That is how I find a specific +word
  • That is how I leave the -word out of the results
  • “That is how I can find the whole phrase”

Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA

The result's identifiers

  • Result code in IS VaVaI

    <a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F23%3A00366854" target="_blank" >RIV/68407700:21240/23:00366854 - isvavai.cz</a>

  • Result on the web

    <a href="https://doi.org/10.1109/MECO58584.2023.10155065" target="_blank" >https://doi.org/10.1109/MECO58584.2023.10155065</a>

  • DOI - Digital Object Identifier

    <a href="http://dx.doi.org/10.1109/MECO58584.2023.10155065" target="_blank" >10.1109/MECO58584.2023.10155065</a>

Alternative languages

  • Result language

    angličtina

  • Original language name

    Evaluation of the Medium-sized Neural Network using Approximative Computations on Zynq FPGA

  • Original language description

    Integrating artificial intelligence technologies into embedded systems requires efficient implementation of neural networks in hardware. The paper presents a Zynq 7020 FPGA implementation and evaluation of a middle-sized dense neural network based on approximate computation by linearly approximated functions. Three famous benchmarks were used for classification accuracy evaluation and hardware testing. We use our highly pipelined neural hardware architecture that takes weights from block RAMs to save logic resources and enables their update from the processing system. The architecture reaches excellent design scalability, allowing us to estimate the number of neurons implemented in programmable logic based on single-neuron resources. We reached nearly full chip utilization while preserving the high clock frequency for the FPGA used.

  • Czech name

  • Czech description

Classification

  • Type

    D - Article in proceedings

  • CEP classification

  • OECD FORD branch

    20206 - Computer hardware and architecture

Result continuities

  • Project

  • Continuities

    I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Others

  • Publication year

    2023

  • Confidentiality

    S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Data specific for result type

  • Article name in the collection

    Proceedings of 2023 12th Mediterranean Conference on Embedded Computing (MECO)

  • ISBN

    979-8-3503-2291-0

  • ISSN

    2637-9511

  • e-ISSN

    2637-9511

  • Number of pages

    4

  • Pages from-to

    1-4

  • Publisher name

    IEEE

  • Place of publication

    Piscataway

  • Event location

    Budva

  • Event date

    Jun 6, 2023

  • Type of event by nationality

    WRD - Celosvětová akce

  • UT code for WoS article