Structural bias in synthesis of sparsely-specified functions

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F24%3A00380769" target="_blank" >RIV/68407700:21240/24:00380769 - isvavai.cz</a>
Result on the web
<a href="https://doi.org/10.1515/itit-2024-0071" target="_blank" >https://doi.org/10.1515/itit-2024-0071</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1515/itit-2024-0071" target="_blank" >10.1515/itit-2024-0071</a>

Result language
angličtina
Original language name
Structural bias in synthesis of sparsely-specified functions
Original language description
Two-level logic minimization is a well-established process that efficiently minimizes functions described in the Sum-of-Products (SOP) form. Current two-level SOP minimizes, like Espresso and Boom, produce optimum or near-optimum results regarding the SOP size. However, in this article we show that an SOP minimization conducted in the standard, multi-output way, significantly worsens the result of the subsequent multi-level synthesis, especially for sparsely-specified functions, regardless of the optimization process and the tool used. In conclusion, we propose using a single-output two-level SOP minimization for sparsely specified functions. In this way, the obtained circuits are sometimes multiple times smaller, while no significant deterioration has been observed for any other functions.
Czech name
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Czech description
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Type
J<sub>imp</sub> - Article in a specialist periodical, which is included in the Web of Science database
CEP classification
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OECD FORD branch
20206 - Computer hardware and architecture

Project
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Continuities
I - Institucionalni podpora na dlouhodoby koncepcni rozvoj vyzkumne organizace

Publication year
2024
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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