Modelling of Thermal Stresses in Printed Circuit Boards

Result code in IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F70883521%3A28140%2F11%3A43866460" target="_blank" >RIV/70883521:28140/11:43866460 - isvavai.cz</a>
Alternative codes found
RIV/70883521:28110/11:43866460
Result on the web
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DOI - Digital Object Identifier
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Result language
angličtina
Original language name
Modelling of Thermal Stresses in Printed Circuit Boards
Original language description
Results of FEM modelling of thermal stress analysis in printed circuit boards are given in the article. It is shown that thermal stress alone is not solely caused by differences in coefficients of thermal expansion of individual layers. The emergence ofthermal stress is subject to both the layered structure of the wall and given boundary conditions, as well as the existence of a temperature gradient in the direction normal to the surface of the wall. A practical application focuses on the issue of recycling of PCB with the effort to achieve separation of layers due to thermal stress. Role modelling of thermal stress in this area lies in predicting the possibility of separation, depending on the type of thermal stress and material parameters.
Czech name
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Czech description
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Project
<a href="/en/project/ED2.1.00%2F03.0089" target="_blank" >ED2.1.00/03.0089: The Centre of Security, Information and Advanced Technologies (CEBIA-Tech)</a><br>
Continuities
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>Z - Vyzkumny zamer (s odkazem do CEZ)

Publication year
2011
Confidentiality
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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