Pure C++ Approach to Optimized Parallel Traversal of Regular Data Structures
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216208%3A11320%2F24%3A10481450" target="_blank" >RIV/00216208:11320/24:10481450 - isvavai.cz</a>
Výsledek na webu
<a href="https://doi.org/10.1145/3649169.3649247" target="_blank" >https://doi.org/10.1145/3649169.3649247</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1145/3649169.3649247" target="_blank" >10.1145/3649169.3649247</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
Pure C++ Approach to Optimized Parallel Traversal of Regular Data Structures
Popis výsledku v původním jazyce
Many computational problems consider memory throughput a performance bottleneck. The problem becomes even more pronounced in the case of parallel platforms, where the ratio between computing elements and memory bandwidth shifts towards computing. Software needs to be attuned to hardware features like cache architectures or memory banks to reach a decent level of performance efficiency. This can be achieved by selecting the right memory layouts for data structures or changing the order of data structure traversal. In this work, we present an abstraction for traversing a set of regular data structures (e.g., multidimensional arrays) that allows the design of traversal-agnostic algorithms. Such algorithms can be adjusted for particular memory layouts of the data structures, semi-automated parallelization, or auto-tuning without altering their internal code. The proposed solution was implemented as an extension of the Noarr library that simplifies a layout-agnostic design of regular data structures. It is implemented entirely using C++ template meta-programming without any nonstandard dependencies, so it is fully compatible with existing compilers, including CUDA NVCC. We evaluate the performance and expressiveness of our approach on the Polybench-C benchmarks.
Název v anglickém jazyce
Pure C++ Approach to Optimized Parallel Traversal of Regular Data Structures
Popis výsledku anglicky
Many computational problems consider memory throughput a performance bottleneck. The problem becomes even more pronounced in the case of parallel platforms, where the ratio between computing elements and memory bandwidth shifts towards computing. Software needs to be attuned to hardware features like cache architectures or memory banks to reach a decent level of performance efficiency. This can be achieved by selecting the right memory layouts for data structures or changing the order of data structure traversal. In this work, we present an abstraction for traversing a set of regular data structures (e.g., multidimensional arrays) that allows the design of traversal-agnostic algorithms. Such algorithms can be adjusted for particular memory layouts of the data structures, semi-automated parallelization, or auto-tuning without altering their internal code. The proposed solution was implemented as an extension of the Noarr library that simplifies a layout-agnostic design of regular data structures. It is implemented entirely using C++ template meta-programming without any nonstandard dependencies, so it is fully compatible with existing compilers, including CUDA NVCC. We evaluate the performance and expressiveness of our approach on the Polybench-C benchmarks.
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
—
OECD FORD obor
10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)
Návaznosti výsledku
Projekt
—
Návaznosti
S - Specificky vyzkum na vysokych skolach
Ostatní
Rok uplatnění
2024
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
Proceedings of the 15th International Workshop on Programming Models and Applications for Multicores and Manycores
ISBN
979-8-4007-0599-1
ISSN
—
e-ISSN
—
Počet stran výsledku
10
Strana od-do
42-51
Název nakladatele
Association for Computing Madinery
Místo vydání
New York, NY, USA
Místo konání akce
Edinburgh
Datum konání akce
3. 3. 2024
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
001182171800005