Accelerating Temporal Verification of Simulink Diagrams Using Satisfiability Modulo Theories

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216224%3A14330%2F16%3A00089030" target="_blank" >RIV/00216224:14330/16:00089030 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1007/s11219-014-9259-x" target="_blank" >http://dx.doi.org/10.1007/s11219-014-9259-x</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/s11219-014-9259-x" target="_blank" >10.1007/s11219-014-9259-x</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Accelerating Temporal Verification of Simulink Diagrams Using Satisfiability Modulo Theories

Popis výsledku v původním jazyce

Automatic verification of programs and computer systems with input variables represents a significant and well-motivated challenge. The case of Simulink diagrams is especially difficult, because there the inputs are read iteratively and the number of input variables is in theory unbounded. We apply the techniques of explicit model checking to account for the temporal (control) aspects of verification and use set-based representation of data, thus handling both sources of non-determinism present in the verification. Two different representations of sets are evaluated in scalability with respect to the range of input variables. Explicit (enumerating) sets are very fast for small ranges but fail to scale. Symbolic sets, represented as first-order formulas in the bit-vector theory and compared using satisfiability modulo theory solvers, scale well to arbitrary (though still bounded) range of input variables.

Název v anglickém jazyce

Accelerating Temporal Verification of Simulink Diagrams Using Satisfiability Modulo Theories

Popis výsledku anglicky

Automatic verification of programs and computer systems with input variables represents a significant and well-motivated challenge. The case of Simulink diagrams is especially difficult, because there the inputs are read iteratively and the number of input variables is in theory unbounded. We apply the techniques of explicit model checking to account for the temporal (control) aspects of verification and use set-based representation of data, thus handling both sources of non-determinism present in the verification. Two different representations of sets are evaluated in scalability with respect to the range of input variables. Explicit (enumerating) sets are very fast for small ranges but fail to scale. Symbolic sets, represented as first-order formulas in the bit-vector theory and compared using satisfiability modulo theory solvers, scale well to arbitrary (though still bounded) range of input variables.

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

IN - Informatika

OECD FORD obor

—

Projekt

<a href="/cs/project/7H13001" target="_blank" >7H13001: Critical System Engineering Acceleration</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Software Quality Journal

ISSN

0963-9314

e-ISSN

—

Svazek periodika

24

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

27

Strana od-do

37-63

Kód UT WoS článku

000369006200004

EID výsledku v databázi Scopus

—