Design and Implementation of a Low Power Area Efficient Bfloat16 based CORDIC Processor

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216275%3A25530%2F22%3A39919616" target="_blank" >RIV/00216275:25530/22:39919616 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9764911/" target="_blank" >https://ieeexplore.ieee.org/document/9764911/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/RADIOELEKTRONIKA54537.2022.9764911" target="_blank" >10.1109/RADIOELEKTRONIKA54537.2022.9764911</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design and Implementation of a Low Power Area Efficient Bfloat16 based CORDIC Processor

Popis výsledku v původním jazyce

Coordinate Rotation Digital Computer (CORDIC) algorithm has a great advantage in hardware based implementation because of its simple architecture. It employs shifter and adder for hardware implementation. The major issue with a CORDIC algorithm is the linear dependence of convergence on the number of iterations. Each iteration performs shift and addition or subtraction operations, due to this there is a trade off between area and delay. Also, the floating-point representation of angles would also increase the area and power. The main aim of this work is to implement a low power and area efficient bfloat16 based on a CORDIC algorithm. The proposed hardware module consumes 3.2x and 3.38x less area and power compared to a single-precision floating-point based CORDIC implementation. The result of the proposed module has been verified on a Zynq evaluation FPGA board.

Název v anglickém jazyce

Design and Implementation of a Low Power Area Efficient Bfloat16 based CORDIC Processor

Popis výsledku anglicky

Coordinate Rotation Digital Computer (CORDIC) algorithm has a great advantage in hardware based implementation because of its simple architecture. It employs shifter and adder for hardware implementation. The major issue with a CORDIC algorithm is the linear dependence of convergence on the number of iterations. Each iteration performs shift and addition or subtraction operations, due to this there is a trade off between area and delay. Also, the floating-point representation of angles would also increase the area and power. The main aim of this work is to implement a low power and area efficient bfloat16 based on a CORDIC algorithm. The proposed hardware module consumes 3.2x and 3.38x less area and power compared to a single-precision floating-point based CORDIC implementation. The result of the proposed module has been verified on a Zynq evaluation FPGA board.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20202 - Communication engineering and systems

Projekt

<a href="/cs/project/LTAIN19100" target="_blank" >LTAIN19100: Vývoj bezkontaktní technologie pro inteligentní ochranu zájmových prostor</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2022 32ND INTERNATIONAL CONFERENCE RADIOELEKTRONIKA (RADIOELEKTRONIKA)

ISBN

978-1-72818-686-3

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

185-190

Název nakladatele

IEEE

Místo vydání

NEW YORK

Místo konání akce

Kosice

Datum konání akce

21. 4. 2022

Typ akce podle státní příslušnosti

CST - Celostátní akce

Kód UT WoS článku

000856002200039