IndiRA: Design and Implementation of a Pipelined RISC-V Processor

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216275%3A25530%2F23%3A39921209" target="_blank" >RIV/00216275:25530/23:39921209 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/10109058" target="_blank" >https://ieeexplore.ieee.org/document/10109058</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/RADIOELEKTRONIKA57919.2023.10109058" target="_blank" >10.1109/RADIOELEKTRONIKA57919.2023.10109058</a>

Jazyk výsledku

angličtina

Název v původním jazyce

IndiRA: Design and Implementation of a Pipelined RISC-V Processor

Popis výsledku v původním jazyce

The development of Machine Learning and IoT technology requires fast processing. RISC-V is an open-source reduced instruction set-based instruction set architecture, and the processor based on this architecture can be modified accordingly. The base integer instruction extension supports the operating system environment and is also suitable for embedded systems. It is a 32-bit instruction extension and is defined as RV32I. In this paper, we propose a 32-bit integer instruction-based RISC-V processor core. The proposed core has a five-stage pipeline, including the optimized arithmetic and logic unit. The instruction fetch stage is merged with the pre-fetch stage dynamic branch prediction into a two-stage pipeline. The processor is implemented using Verilog HDL, and the resource utilization is verified for FPGA. The results show that the proposed module performs 30% better than the best-performing processor (considering operating frequency) and showed a 17.6% improvement in the proposed core.

Název v anglickém jazyce

IndiRA: Design and Implementation of a Pipelined RISC-V Processor

Popis výsledku anglicky

The development of Machine Learning and IoT technology requires fast processing. RISC-V is an open-source reduced instruction set-based instruction set architecture, and the processor based on this architecture can be modified accordingly. The base integer instruction extension supports the operating system environment and is also suitable for embedded systems. It is a 32-bit instruction extension and is defined as RV32I. In this paper, we propose a 32-bit integer instruction-based RISC-V processor core. The proposed core has a five-stage pipeline, including the optimized arithmetic and logic unit. The instruction fetch stage is merged with the pre-fetch stage dynamic branch prediction into a two-stage pipeline. The processor is implemented using Verilog HDL, and the resource utilization is verified for FPGA. The results show that the proposed module performs 30% better than the best-performing processor (considering operating frequency) and showed a 17.6% improvement in the proposed core.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/EF17_049%2F0008394" target="_blank" >EF17_049/0008394: Spolupráce Univerzity Pardubice a aplikační sféry v aplikačně orientovaném výzkumu lokačních, detekčních a simulačních systémů pro dopravní a přepravní procesy (PosiTrans)</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

33rd International Conference Radioelektronika, Radioelektronika 2023

ISBN

979-8-3503-9834-2

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

—

Název nakladatele

IEEE (Institute of Electrical and Electronics Engineers)

Místo vydání

New York

Místo konání akce

Pardubice

Datum konání akce

19. 4. 2023

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000990505700032