Serial Communication Peripheries Development in FPGA

Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F09%3APU80924" target="_blank" >RIV/00216305:26220/09:PU80924 - isvavai.cz</a>
Výsledek na webu
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DOI - Digital Object Identifier
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Jazyk výsledku
čeština
Název v původním jazyce
Serial Communication Peripheries Development in FPGA
Popis výsledku v původním jazyce
This project is about periphery, which from parallel input signals make one output serial signal. This serial signal contains start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count isset with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. After parity bit there is one stop bit or there are two stop bits. The periphery is programmed in VHDL language and implemented in FPGA device. After simulation theimplementation was realized in Xilinx ISE WebPACK and tested in real time.
Název v anglickém jazyce
Serial Communication Peripheries Development in FPGA
Popis výsledku anglicky
This project is about periphery, which from parallel input signals make one output serial signal. This serial signal contains start bit, the next are data bits, parity bit and stop bit or two stop bits. Data bits are variables. It is mean their count isset with two input signals called Dat0 and Dat1. We can secure data bits with parity bit. After parity bit there is one stop bit or there are two stop bits. The periphery is programmed in VHDL language and implemented in FPGA device. After simulation theimplementation was realized in Xilinx ISE WebPACK and tested in real time.

Rok uplatnění
2009
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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