Advanced Mapping Techniques for Digital Signal Processors

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F16%3APU120950" target="_blank" >RIV/00216305:26220/16:PU120950 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/ICCES.2018.8639186" target="_blank" >http://dx.doi.org/10.1109/ICCES.2018.8639186</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ICCES.2018.8639186" target="_blank" >10.1109/ICCES.2018.8639186</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Advanced Mapping Techniques for Digital Signal Processors

Popis výsledku v původním jazyce

This paper is focused on the hardware modeling and mapping the algorithms on the many-, multi -core platforms, such as TMS320C6678 digital signal processor (DSP) with the very long instruction word (VLIW) architecture. The main methods to develop an application for the target processor combine high- and/or low-level programming languages. Although the hardware capabilities of the nowadays processors and compilers are persistently increasing, the programmers common practice is to hand-optimize critical parts of the digital signal processing algorithms in assembly code. In the paper the benefit of the auxiliary tool for generating of semi-optimal codes for the DSP is presented. The functions for basic vector operations (addition, multiplication, and dot product) were proposed by this tool and the computing performances were compared to the corresponding functions from the TMS320C6000 DSP Library (DSPLIB). Comparing the functions' duration, the proposed routines achieve the average acceleration of 24 CPU cycles.

Název v anglickém jazyce

Advanced Mapping Techniques for Digital Signal Processors

Popis výsledku anglicky

This paper is focused on the hardware modeling and mapping the algorithms on the many-, multi -core platforms, such as TMS320C6678 digital signal processor (DSP) with the very long instruction word (VLIW) architecture. The main methods to develop an application for the target processor combine high- and/or low-level programming languages. Although the hardware capabilities of the nowadays processors and compilers are persistently increasing, the programmers common practice is to hand-optimize critical parts of the digital signal processing algorithms in assembly code. In the paper the benefit of the auxiliary tool for generating of semi-optimal codes for the DSP is presented. The functions for basic vector operations (addition, multiplication, and dot product) were proposed by this tool and the computing performances were compared to the corresponding functions from the TMS320C6000 DSP Library (DSPLIB). Comparing the functions' duration, the proposed routines achieve the average acceleration of 24 CPU cycles.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

16th IEEE International Symposium on Signal Processing and Information Technology

ISBN

978-1-5090-2902-0

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

1-4

Název nakladatele

IEEE

Místo vydání

Cyprus

Místo konání akce

Limassol

Datum konání akce

12. 12. 2016

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000406122500039