Direct Learning Architecture For Digital Predistortion with Real-Valued Feedback

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F18%3APU128906" target="_blank" >RIV/00216305:26220/18:PU128906 - isvavai.cz</a>

Výsledek na webu

—

DOI - Digital Object Identifier

—

Jazyk výsledku

angličtina

Název v původním jazyce

Direct Learning Architecture For Digital Predistortion with Real-Valued Feedback

Popis výsledku v původním jazyce

The power efficiency is a key parameter of modern comunication systems. Efficient nonlinear power amplifiers are linearised using digital predistorters. Conventional predistorters require two ADCs in the feedback. In this paper we have proposed a modification of the direct learning architecture using solely one ADC in the feedback and an RF mixer instead of a quadrature mixer. This allows us to minimise the system complexity and power consumtion and maximise the efficiency. The proposed architecture has been verified experimentally and compared to the conventional digital predistorters. We have shown that it can achieve same linearisation performance as the conventional architecture with two ADCs. Moreover the proposed method outperformed the conventional DPD with indirect learning architecture.

Název v anglickém jazyce

Direct Learning Architecture For Digital Predistortion with Real-Valued Feedback

Popis výsledku anglicky

The power efficiency is a key parameter of modern comunication systems. Efficient nonlinear power amplifiers are linearised using digital predistorters. Conventional predistorters require two ADCs in the feedback. In this paper we have proposed a modification of the direct learning architecture using solely one ADC in the feedback and an RF mixer instead of a quadrature mixer. This allows us to minimise the system complexity and power consumtion and maximise the efficiency. The proposed architecture has been verified experimentally and compared to the conventional digital predistorters. We have shown that it can achieve same linearisation performance as the conventional architecture with two ADCs. Moreover the proposed method outperformed the conventional DPD with indirect learning architecture.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 24th Conference STUDENT EEICT 2018

ISBN

978-80-214-5614-3

ISSN

—

e-ISSN

—

Počet stran výsledku

5

Strana od-do

332-336

Název nakladatele

Brno University of Technology, Faculty of Electrical Engineering and Communication

Místo vydání

Brno, Czech Republic

Místo konání akce

Brno

Datum konání akce

27. 4. 2017

Typ akce podle státní příslušnosti

CST - Celostátní akce

Kód UT WoS článku

—