Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F20%3APU137627" target="_blank" >RIV/00216305:26220/20:PU137627 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9244145" target="_blank" >https://ieeexplore.ieee.org/document/9244145</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ACCESS.2020.3034665" target="_blank" >10.1109/ACCESS.2020.3034665</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

Popis výsledku v původním jazyce

This work describes design process toward fully analogue binary memory where two coupled piecewise-linear (PWL) resistors are implemented using novel network topology with voltage gain amplifiers (VGA). These versatile active devices allow slopes of individual segments of ampere-voltage (AV) characteristics associated with PWL two-terminals to be electronically adjustable via external DC voltage. Numerical analysis of designed memory cell covers all mandatory parts: phase portraits, calculation of the largest Lyapunov exponent (LLE), basins of attraction for the typical strange attractors, and high resolution circuit-oriented bifurcation sequences. A transition from the stable states toward chaotic regime through metastability is proved via real measurement. The robustness of the generated chaotic attractors is verified by captured oscilloscope screenshots.

Název v anglickém jazyce

Binary Memory Implemented by Using Variable Gain Amplifiers With Multipliers

Popis výsledku anglicky

This work describes design process toward fully analogue binary memory where two coupled piecewise-linear (PWL) resistors are implemented using novel network topology with voltage gain amplifiers (VGA). These versatile active devices allow slopes of individual segments of ampere-voltage (AV) characteristics associated with PWL two-terminals to be electronically adjustable via external DC voltage. Numerical analysis of designed memory cell covers all mandatory parts: phase portraits, calculation of the largest Lyapunov exponent (LLE), basins of attraction for the typical strange attractors, and high resolution circuit-oriented bifurcation sequences. A transition from the stable states toward chaotic regime through metastability is proved via real measurement. The robustness of the generated chaotic attractors is verified by captured oscilloscope screenshots.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/GA19-22248S" target="_blank" >GA19-22248S: Deterministické, chaotické a stochastické jevy v sub-mikronových integrovaných strukturách</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Access

ISSN

2169-3536

e-ISSN

—

Svazek periodika

8

Číslo periodika v rámci svazku

1

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

11

Strana od-do

197276-197286

Kód UT WoS článku

000589749900001

EID výsledku v databázi Scopus

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