Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F21%3APU141287" target="_blank" >RIV/00216305:26220/21:PU141287 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9465156" target="_blank" >https://ieeexplore.ieee.org/document/9465156</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ACCESS.2021.3092525" target="_blank" >10.1109/ACCESS.2021.3092525</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

Popis výsledku v původním jazyce

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

Název v anglickém jazyce

Analog Multipliers-Based Double Output Voltage Phase Detector for Low-Frequency Demodulation of Frequency Modulated Signals

Popis výsledku anglicky

This work deals with the design of a simple double output voltage phase detector, using a specific type of analog multiplier, and its application in a frequency demodulator. The design of active parts was performed in Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m 1.8 V CMOS technology. The intention is devoted to design the circuitry in such a way to avoid low-frequency signal processing with large values of capacities that are not available in case of on-chip implementation. The idea consists in the processing of significantly faster signal (tens of kHz) carrying modulated low frequency information. Then the coupling capacity may have significantly smaller value. The operation of the demodulator was tested for carrier frequency 50 kHz and for modulation signal with frequency of 10 Hz and 500 Hz. Differences of these frequencies approximately determine the values of capacitors required for AC coupling. Simulations (Cadence Spectre simulator) as well as experimental measurement, using fabricated ASIC prototypes, are provided to verify the proposed circuits in both the time and frequency domain.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/GA19-22248S" target="_blank" >GA19-22248S: Deterministické, chaotické a stochastické jevy v sub-mikronových integrovaných strukturách</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2021

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE Access

ISSN

2169-3536

e-ISSN

—

Svazek periodika

9

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

17

Strana od-do

93062-93078

Kód UT WoS článku

000673922100001

EID výsledku v databázi Scopus

2-s2.0-85112493531