Designing series of fractional-order elements

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F21%3APU142840" target="_blank" >RIV/00216305:26220/21:PU142840 - isvavai.cz</a>

Výsledek na webu

<a href="https://link.springer.com/content/pdf/10.1007/s10470-021-01811-4.pdf" target="_blank" >https://link.springer.com/content/pdf/10.1007/s10470-021-01811-4.pdf</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/s10470-021-01811-4" target="_blank" >10.1007/s10470-021-01811-4</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Designing series of fractional-order elements

Popis výsledku v původním jazyce

In this paper we propose an efficient approach to design fractional-order elements' (FOEs) series, while using a very limited set of "seed" FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order alpha being in the range [-2,2]. The proposed circuit may simply be extended to design fractional-order elements from wider range of alpha to follow designers' requirements. To show the efficiency of the described technique, the use of only up to two "seed" FOEs with properly selected fractional order alpha seed as passive elements results in the design of a series of 17 FOEs with different alpha being in the range [-2,2]. Cadence post-layout simulation results are presented that prove operability and robustness of our design concept. Basic fractional 1.75-order low-pass filter is also presented to show the utilization of a FOE being implemented by the proposed GIC.

Název v anglickém jazyce

Designing series of fractional-order elements

Popis výsledku anglicky

In this paper we propose an efficient approach to design fractional-order elements' (FOEs) series, while using a very limited set of "seed" FOEs. The proposed approach follows the idea of general immittance inverter/converter, whereas a suitable circuit solution employing operational transconductance amplifiers is also presented and can be used for the design of grounded FOEs with the fractional order alpha being in the range [-2,2]. The proposed circuit may simply be extended to design fractional-order elements from wider range of alpha to follow designers' requirements. To show the efficiency of the described technique, the use of only up to two "seed" FOEs with properly selected fractional order alpha seed as passive elements results in the design of a series of 17 FOEs with different alpha being in the range [-2,2]. Cadence post-layout simulation results are presented that prove operability and robustness of our design concept. Basic fractional 1.75-order low-pass filter is also presented to show the utilization of a FOE being implemented by the proposed GIC.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/GA19-24585S" target="_blank" >GA19-24585S: Syntéza elektrických fantomů věrně popisující fraktální impedanční chování reálných systémů</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2021

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING

ISSN

0925-1030

e-ISSN

1573-1979

Svazek periodika

106

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

NL - Nizozemsko

Počet stran výsledku

11

Strana od-do

553-563

Kód UT WoS článku

000626344200001

EID výsledku v databázi Scopus

2-s2.0-85102287977