Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals from Sensors

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F24%3APU151753" target="_blank" >RIV/00216305:26220/24:PU151753 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/10648767" target="_blank" >https://ieeexplore.ieee.org/document/10648767</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TIM.2024.3427752" target="_blank" >10.1109/TIM.2024.3427752</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals from Sensors

Popis výsledku v původním jazyce

Phase-Locked Loops (PLLs) are versatile electronic circuits that, among others, are used in various sensor applications (e.g., medical) for their ability to generate stable and precise clock signals. This paper introduces a novel PLL-based frequency demodulation system designed for processing very slow signals, ranging from a few Hz to several hundreds of Hz, with amplitudes in the order of several hundreds of millivolts. The system incorporates specialized analog multipliers tailored for essential PLL components, including the voltage-controlled oscillator, phase detector, loop filter with variable DC offset, and base-band filter, all optimized for the purpose of frequency demodulation. These multipliers were fabricated using the TSMC 0.18 µm, 1.8 V CMOS process. The primary design objectives are simplicity, reduced complexity, low power consumption (merely 15 mW), and versatility for applications in sensing engineering. To validate the functionality of the proposed PLL system under practical conditions, we present an example of electrocardiogram signal demodulation, demonstrating its operational performance.

Název v anglickém jazyce

Design of Phase-Locked Loop Using Special Analog Multipliers and Voltage Buffers: Demodulation of Transposed Signals from Sensors

Popis výsledku anglicky

Phase-Locked Loops (PLLs) are versatile electronic circuits that, among others, are used in various sensor applications (e.g., medical) for their ability to generate stable and precise clock signals. This paper introduces a novel PLL-based frequency demodulation system designed for processing very slow signals, ranging from a few Hz to several hundreds of Hz, with amplitudes in the order of several hundreds of millivolts. The system incorporates specialized analog multipliers tailored for essential PLL components, including the voltage-controlled oscillator, phase detector, loop filter with variable DC offset, and base-band filter, all optimized for the purpose of frequency demodulation. These multipliers were fabricated using the TSMC 0.18 µm, 1.8 V CMOS process. The primary design objectives are simplicity, reduced complexity, low power consumption (merely 15 mW), and versatility for applications in sensing engineering. To validate the functionality of the proposed PLL system under practical conditions, we present an example of electrocardiogram signal demodulation, demonstrating its operational performance.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE TRANSACTIONS ON INSTRUMENTATION AND MEASUREMENT

ISSN

0018-9456

e-ISSN

1557-9662

Svazek periodika

2024

Číslo periodika v rámci svazku

73

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

12

Strana od-do

1-12

Kód UT WoS článku

001329048600020

EID výsledku v databázi Scopus

2-s2.0-85202776805