Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26220%2F26%3A0197765" target="_blank" >RIV/00216305:26220/26:0197765 - isvavai.cz</a>

Výsledek na webu

<a href="https://link.springer.com/article/10.1038/s41598-025-96539-w" target="_blank" >https://link.springer.com/article/10.1038/s41598-025-96539-w</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1038/s41598-025-96539-w" target="_blank" >10.1038/s41598-025-96539-w</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Popis výsledku v původním jazyce

The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.

Název v anglickém jazyce

Design, synthesis and simulation of fractional-order element using MOS transistors as distributed resistive capacitive devices

Popis výsledku anglicky

The article presents a synthesis method to design electrical circuit elements with fractional-order impedance, referred to as a Fractional-Order Element (FOE) or Fractor, that can be implemented by Metal-Oxide-Semiconductor (MOS) transistors. This provides an approach to realize this class of device using current integrated circuit manufacturing technologies. For this synthesis MOS transistors are treated as uniform distributed resistive-capacitive layer structures. The synthesis approach adopts a genetic algorithm to generate the MOS structures interconnections and dimensions to realize an FOE with user-defined constant input admittance phase, allowed ripple deviations, and target frequency range. A graphical user interface for the synthesis process is presented to support its wider adoption. We synthetized and present FOEs with admittance phase from 5 degrees to 85 degrees. The design approach is validated using Cadence post-layout simulations of an FOE design with admittance phase of 74 +/- 1 degrees realized using native n-channel MOS devices in TSMC 65 nm technology. Overall, the post-layout simulations demonstrate magnitude and phase errors less than 0.5% and 0.1 degrees, respectively, compared to the synthesis expected values in the frequency band from 1 kHz to 10 MHz. This supports that the design approach is appropriate for the future fabrication and validation of FOEs using this process technology.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

<a href="/cs/project/GA23-06070S" target="_blank" >GA23-06070S: Základní výzkum v návrhu CMOS prvků fraktálního řádu</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2025

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Scientific Reports

ISSN

2045-2322

e-ISSN

—

Svazek periodika

15

Číslo periodika v rámci svazku

4

Stát vydavatele periodika

GB - Spojené království Velké Británie a Severního Irska

Počet stran výsledku

18

Strana od-do

—

Kód UT WoS článku

001478305300004

EID výsledku v databázi Scopus

2-s2.0-105003691263