Performance Prediction Model of Bus-Based Shared Memory Architectures

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Performance Prediction Model of Bus-Based Shared Memory Architectures

Popis výsledku v původním jazyce

It is shown that cache-coherent bus-based multiprocessor simulation can be implemented using message passing and few shared variables, at least in the case of an atomic bus and known coherence protocols. Data request and write-back bus transactions are generating messages to a shared memory server process, shared variables are used only for synchronization. A change in their values by one process is visible simultaneously to other processes, where it triggers invalidation/update actions. Models of variious locks and barriers are described and the simulation-based performance prediction using Transim tool is illustrated on the example of parallel FFT benchmark in OpenMP. Multiprocessor hw, sw, and mapping to one another is described in Transim languagethat supports synchronous message passing as well as shared variables. Accuracy of prediction (8 %) has been satisfactory in the benchmark under test and may continue to be so in other benchmarks.

Název v anglickém jazyce

Performance Prediction Model of Bus-Based Shared Memory Architectures

Popis výsledku anglicky

It is shown that cache-coherent bus-based multiprocessor simulation can be implemented using message passing and few shared variables, at least in the case of an atomic bus and known coherence protocols. Data request and write-back bus transactions are generating messages to a shared memory server process, shared variables are used only for synchronization. A change in their values by one process is visible simultaneously to other processes, where it triggers invalidation/update actions. Models of variious locks and barriers are described and the simulation-based performance prediction using Transim tool is illustrated on the example of parallel FFT benchmark in OpenMP. Multiprocessor hw, sw, and mapping to one another is described in Transim languagethat supports synchronous message passing as well as shared variables. Accuracy of prediction (8 %) has been satisfactory in the benchmark under test and may continue to be so in other benchmarks.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2002

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of 36th International Conference MOSIS'02 Modelling and Simulation of Systems

ISBN

80-85988-71-2

ISSN

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e-ISSN

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Počet stran výsledku

8

Strana od-do

273-280

Název nakladatele

Neuveden

Místo vydání

Ostrava

Místo konání akce

Rožnov pod Radhoštěm

Datum konání akce

22. 4. 2002

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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