Verifying Parametrised Hardware Designs Via Counter Automata

Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU70924" target="_blank" >RIV/00216305:26230/08:PU70924 - isvavai.cz</a>
Výsledek na webu
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DOI - Digital Object Identifier
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Jazyk výsledku
angličtina
Název v původním jazyce
Verifying Parametrised Hardware Designs Via Counter Automata
Popis výsledku v původním jazyce
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of such designs to counter automata and on exploiting the recent advances achievedin the area of their automated formal verification. We have implemented the proposed translation. Using one of the state-of-the-art tools for verification of counter automata, we were then able to verify several non-trivial properties of parametrised VHDL components, including a real-life one.
Název v anglickém jazyce
Verifying Parametrised Hardware Designs Via Counter Automata
Popis výsledku anglicky
The paper presents a new approach to formal verification of generic (i.e. parametrised) hardware designs specified in VHDL. The proposed approach is based on a translation of such designs to counter automata and on exploiting the recent advances achievedin the area of their automated formal verification. We have implemented the proposed translation. Using one of the state-of-the-art tools for verification of counter automata, we were then able to verify several non-trivial properties of parametrised VHDL components, including a real-life one.

Rok uplatnění
2008
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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