Síťová sonda pro flexibilní monitorování

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU76725" target="_blank" >RIV/00216305:26230/08:PU76725 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/63839172:_____/08:00000929

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Network Probe for Flexible Flow Monitoring

Popis výsledku v původním jazyce

Research in measurement and monitoring of Internet traffic is evolving rapidly but network tools that would be able to follow it are still rare. New approaches and methods are often tested in offline environment or on low-speed links using software solutions, but consecutive real-time deployment on high-speed links is missing.&nbsp; In this context we propose a flexible network probe which is a foundation stone for further network measurement and monitoring. The architecture of the probe is based on a network acceleration card with Field-Programmable Gate Arrays (FPGA) and a host computer.&nbsp; The configuration for FPGA chips is automatically generated by a configuration program according to the user's definition of the monitored values in order to save hardware resources and increase the throughput. The definition of the monitoring process is described using XML, transformed to VHDL and synthesized. This enables the probe to gain any information about network traffic, assign it to t

Název v anglickém jazyce

Network Probe for Flexible Flow Monitoring

Popis výsledku anglicky

Research in measurement and monitoring of Internet traffic is evolving rapidly but network tools that would be able to follow it are still rare. New approaches and methods are often tested in offline environment or on low-speed links using software solutions, but consecutive real-time deployment on high-speed links is missing.&nbsp; In this context we propose a flexible network probe which is a foundation stone for further network measurement and monitoring. The architecture of the probe is based on a network acceleration card with Field-Programmable Gate Arrays (FPGA) and a host computer.&nbsp; The configuration for FPGA chips is automatically generated by a configuration program according to the user's definition of the monitored values in order to save hardware resources and increase the throughput. The definition of the monitoring process is described using XML, transformed to VHDL and synthesized. This enables the probe to gain any information about network traffic, assign it to t

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2008

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proc. of 2008 IEEE Design and Diagnostics of Electronic Circuits and Systems Workshop

ISBN

978-1-4244-2276-0

ISSN

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e-ISSN

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Počet stran výsledku

6

Strana od-do

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Název nakladatele

IEEE Computer Society

Místo vydání

Bratislava

Místo konání akce

Bratislava

Datum konání akce

16. 4. 2008

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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