Automatizovaný návrh filtrů v FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F08%3APU78070" target="_blank" >RIV/00216305:26230/08:PU78070 - isvavai.cz</a>

Výsledek na webu

—

DOI - Digital Object Identifier

—

Jazyk výsledku

angličtina

Název v původním jazyce

Towards Automatic Design of Competitive Image Filters in FPGAs

Popis výsledku v původním jazyce

This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the salt and pepper noise of high intensity. An evolutionary algorithm (EA) is utilized to find a set of image filters which can be employed in abank of image filters. <br><br>The main advantage of this approach is that the bank of evolutionary designed filters requires four times less resources on a chip in comparison with the adaptive median filter while the<br>visual quality of filtering is preserved. The proposed solution also exhibits a very good behavior for the impulse bursts noise.<br><br>In order to design image filters in reasonable time, an FPGA-based evolutionary platform is<br>utilized. The proposed platform is based on the implementation<br>of a search algorithm in the PowerPC processor which is available in Xilinx<br>Virtex II Pro and newer FPGAs.<br>As the search algorithm as well as the evaluation of candidate solution runs in FPGA, <br>the evolutionary design o

Název v anglickém jazyce

Towards Automatic Design of Competitive Image Filters in FPGAs

Popis výsledku anglicky

This paper presents a new approach to the FPGA implementation of image filters which are utilized to remove the salt and pepper noise of high intensity. An evolutionary algorithm (EA) is utilized to find a set of image filters which can be employed in abank of image filters. <br><br>The main advantage of this approach is that the bank of evolutionary designed filters requires four times less resources on a chip in comparison with the adaptive median filter while the<br>visual quality of filtering is preserved. The proposed solution also exhibits a very good behavior for the impulse bursts noise.<br><br>In order to design image filters in reasonable time, an FPGA-based evolutionary platform is<br>utilized. The proposed platform is based on the implementation<br>of a search algorithm in the PowerPC processor which is available in Xilinx<br>Virtex II Pro and newer FPGAs.<br>As the search algorithm as well as the evaluation of candidate solution runs in FPGA, <br>the evolutionary design o

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

—

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2008

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of Junior Scientist Conference 2008

ISBN

978-3-200-01612-5

ISSN

—

e-ISSN

—

Počet stran výsledku

2

Strana od-do

—

Název nakladatele

Technical University Wien

Místo vydání

Vienna

Místo konání akce

Vídeň

Datum konání akce

16. 11. 2008

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

—