The Design of On-line Checkers and Their Use in Verification and Testing

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F09%3APU82660" target="_blank" >RIV/00216305:26230/09:PU82660 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

The Design of On-line Checkers and Their Use in Verification and Testing

Popis výsledku v původním jazyce

</a></a></a><i>In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. </i></a></a></a><i>The results and compare of both methodologies are described.</i></a><i> The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.</i>

Název v anglickém jazyce

The Design of On-line Checkers and Their Use in Verification and Testing

Popis výsledku anglicky

</a></a></a><i>In the article, a survey of our research activities the goal of which is to develop a methodology allowing to design on-line checkers for digital components and communication protocols are described. First, our experiments with PSL language and FoCs tool are demonstrated for simple RT circuits and communication protocols. It is shown how PSL can be used to describe conditions to be checked by an on-line checker of a digital component. It is demonstrated that on-line checkers generated from PSL description demand more sources than the unit under check which is seen as unacceptable result. The principle of our methodology for generating VHDL descriptions of hardware checkers from the formal model is presented, too. </i></a></a></a><i>The results and compare of both methodologies are described.</i></a><i> The possibilities of utilizing these approaches in the design of Fault Tolerant Systems are described in conclusion.</i>

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2009

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Acta Electrotechnica et Informatica

ISSN

1335-8243

e-ISSN

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Svazek periodika

2009

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

SK - Slovenská republika

Počet stran výsledku

8

Strana od-do

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Kód UT WoS článku

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EID výsledku v databázi Scopus

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