Design and Debugging of Parallel Architectures Using the ISAC Language

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Design and Debugging of Parallel Architectures Using the ISAC Language

Popis výsledku v původním jazyce

Trend of nowadays embedded systems is placing more than one application-specific instruction set processor (ASIP) on one chip (multi-processor systems on a chip). This allows parallel processing of multimedia and network applications, where input is usually a data stream. Each of these processors is highly optimized for a specific task. Other forms of suitable parallel architectures are very long instruction word processors (VLIW) and multi-core processors. These parallel architectures are often used inmulti-processor systems on a chip.<br><br>Architecture description languages (ADL) are very effective for <br>description of simple processors. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in these languages. Therefore, <br>we introduce new constructions of an architecture description language ISAC allowing easy and fast prototyping of such processors and systems.<br>

Název v anglickém jazyce

Design and Debugging of Parallel Architectures Using the ISAC Language

Popis výsledku anglicky

Trend of nowadays embedded systems is placing more than one application-specific instruction set processor (ASIP) on one chip (multi-processor systems on a chip). This allows parallel processing of multimedia and network applications, where input is usually a data stream. Each of these processors is highly optimized for a specific task. Other forms of suitable parallel architectures are very long instruction word processors (VLIW) and multi-core processors. These parallel architectures are often used inmulti-processor systems on a chip.<br><br>Architecture description languages (ADL) are very effective for <br>description of simple processors. However, support for description of parallel architectures and multi-processor systems is very low or completely missing in these languages. Therefore, <br>we introduce new constructions of an architecture description language ISAC allowing easy and fast prototyping of such processors and systems.<br>

Druh

D - Stať ve sborníku

CEP obor

IN - Informatika

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2010

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings ot the Annual International Conference on Advanced Distributed and Parallel Computing and Real-Time and Embedded Systems

ISBN

978-981-08-7656-2

ISSN

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e-ISSN

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Počet stran výsledku

372

Strana od-do

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Název nakladatele

Global Science & Technology Forum

Místo vydání

Singapore

Místo konání akce

Singapore

Datum konání akce

1. 11. 2010

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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