Towards Efficient Field Programmeable Pattern Matching Array
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F15%3APU116982" target="_blank" >RIV/00216305:26230/15:PU116982 - isvavai.cz</a>
Výsledek na webu
<a href="http://dx.doi.org/10.1109/DSD.2015.97" target="_blank" >http://dx.doi.org/10.1109/DSD.2015.97</a>
DOI - Digital Object Identifier
<a href="http://dx.doi.org/10.1109/DSD.2015.97" target="_blank" >10.1109/DSD.2015.97</a>
Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
Towards Efficient Field Programmeable Pattern Matching Array
Popis výsledku v původním jazyce
The automata processor, new architecture for pattern matching was introduced recently. We recognize it as pioneer of new class of field programmable circuits and name it as Field Programmable Pattern Matching Array. In this paper, we investigate enhancement of the architecture. We propose usage of fixed deterministic unit from the NFA-Split architecture as new hard block. Construction process from set of regular expressions via dual position automaton to final partition on deterministic and nondeterministic parts is described. Moreover, we investigate efficiency of deterministic units based on dual position automation. Since the deterministic unit can implement finite automaton without structural restrictions we investigated usage of unrestricted finite automaton for DU and dual position automaton for parts mapped to basic FPPMA elements. According to the results the proposed DU based on unrestricted finite automaton utilizes up to 42.43% less State-transition elements than the deterministic unit based on dual position automaton. According to the results utilization of the deterministic units provides significant reduction of FPPMA resources for particular sets of REs. For example, State-transition elements were reduced by more than 71% for the spyware-put Snort module.
Název v anglickém jazyce
Towards Efficient Field Programmeable Pattern Matching Array
Popis výsledku anglicky
The automata processor, new architecture for pattern matching was introduced recently. We recognize it as pioneer of new class of field programmable circuits and name it as Field Programmable Pattern Matching Array. In this paper, we investigate enhancement of the architecture. We propose usage of fixed deterministic unit from the NFA-Split architecture as new hard block. Construction process from set of regular expressions via dual position automaton to final partition on deterministic and nondeterministic parts is described. Moreover, we investigate efficiency of deterministic units based on dual position automation. Since the deterministic unit can implement finite automaton without structural restrictions we investigated usage of unrestricted finite automaton for DU and dual position automaton for parts mapped to basic FPPMA elements. According to the results the proposed DU based on unrestricted finite automaton utilizes up to 42.43% less State-transition elements than the deterministic unit based on dual position automaton. According to the results utilization of the deterministic units provides significant reduction of FPPMA resources for particular sets of REs. For example, State-transition elements were reduced by more than 71% for the spyware-put Snort module.
Klasifikace
Druh
D - Stať ve sborníku
CEP obor
—
OECD FORD obor
20206 - Computer hardware and architecture
Návaznosti výsledku
Projekt
<a href="/cs/project/ED1.1.00%2F02.0070" target="_blank" >ED1.1.00/02.0070: Centrum excelence IT4Innovations</a><br>
Návaznosti
P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach
Ostatní
Rok uplatnění
2015
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů
Údaje specifické pro druh výsledku
Název statě ve sborníku
Proceedings of the 18th Euromicro Conference on Digital Systems Design
ISBN
978-1-4673-8035-5
ISSN
—
e-ISSN
—
Počet stran výsledku
8
Strana od-do
1-8
Název nakladatele
IEEE Computer Society
Místo vydání
Funchal
Místo konání akce
Funchal
Datum konání akce
26. 8. 2015
Typ akce podle státní příslušnosti
WRD - Celosvětová akce
Kód UT WoS článku
000382382300001