On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F16%3APU121652" target="_blank" >RIV/00216305:26230/16:PU121652 - isvavai.cz</a>

Výsledek na webu

<a href="http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7814012" target="_blank" >http://ieeexplore.ieee.org/stamp/stamp.jsp?arnumber=7814012</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/Austrochip.2016.020" target="_blank" >10.1109/Austrochip.2016.020</a>

Jazyk výsledku

angličtina

Název v původním jazyce

On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC

Popis výsledku v původním jazyce

The paper deals with a novel method of modeling and analysis of software interrupt managers for event-driven embedded systems by means of the stochastic timed automata and statistical model checking instruments. The above-mentioned system is typically formed of a real-time part expected to produce correct responses and meet all predetermined timing constraints at runtime, even in adverse conditions such as an excessive rate of events caused by interrupts. Because of the asynchronnous nature of interrupts, their impact to the system being interrupted must be modeled and analyzed very carefully for various interrupt scenarios - either using classical analytical/formal approaches able to cover systems and interrupts with deterministic behavior or using probablistic ones able to deal with a stochastic behavior too. The paper is focused to the latter (probabilistic) approaches to show a style of such a modeling and show how and that both the analysis phase of a system can be facilitated and the information about a system behavior under particular configuration/scenarios can be produced using the statistical model checking instruments.

Název v anglickém jazyce

On Analysis of Software Interrupt Limiters for Embedded Systems by Means of UPPAAL SMC

Popis výsledku anglicky

The paper deals with a novel method of modeling and analysis of software interrupt managers for event-driven embedded systems by means of the stochastic timed automata and statistical model checking instruments. The above-mentioned system is typically formed of a real-time part expected to produce correct responses and meet all predetermined timing constraints at runtime, even in adverse conditions such as an excessive rate of events caused by interrupts. Because of the asynchronnous nature of interrupts, their impact to the system being interrupted must be modeled and analyzed very carefully for various interrupt scenarios - either using classical analytical/formal approaches able to cover systems and interrupts with deterministic behavior or using probablistic ones able to deal with a stochastic behavior too. The paper is focused to the latter (probabilistic) approaches to show a style of such a modeling and show how and that both the analysis phase of a system can be facilitated and the information about a system behavior under particular configuration/scenarios can be produced using the statistical model checking instruments.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2016

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 24th Austrian Workshop on Microelectronics

ISBN

978-1-5090-1040-0

ISSN

—

e-ISSN

—

Počet stran výsledku

6

Strana od-do

45-50

Název nakladatele

IEEE Computer Society Press

Místo vydání

Villach

Místo konání akce

Villach

Datum konání akce

19. 10. 2016

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

000404429300009