Fault Tolerance in HLS for the Purposes of Reliable System Design Automation

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130750" target="_blank" >RIV/00216305:26230/18:PU130750 - isvavai.cz</a>

Výsledek na webu

<a href="http://www.fit.vutbr.cz/research/pubs/all.php?id=11743" target="_blank" >http://www.fit.vutbr.cz/research/pubs/all.php?id=11743</a>

DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Fault Tolerance in HLS for the Purposes of Reliable System Design Automation

Popis výsledku v původním jazyce

In the presentation, existing method to insert redundancy into HLS-generated systems will be briefly described alongside with its improvement in the form of a majority function selection. We found out that the type of the majority function affects not only the resulting reliability, but also the resources consumption. The presentation also addresses the level of redundancy selection, as we evaluated various numbers of redundant modules with multiple fault occurrences. The case study experiments are carried out with our robot verification platform utilizing the so-called left-hand algorithm and fault injection into a Field Programmable Gate Array (FPGA) implementing the robot controller. This approach is not limited to FPGAs, however, we use an FPGA technology during the evaluation for its wide range of applications and its versatility.

Název v anglickém jazyce

Fault Tolerance in HLS for the Purposes of Reliable System Design Automation

Popis výsledku anglicky

In the presentation, existing method to insert redundancy into HLS-generated systems will be briefly described alongside with its improvement in the form of a majority function selection. We found out that the type of the majority function affects not only the resulting reliability, but also the resources consumption. The presentation also addresses the level of redundancy selection, as we evaluated various numbers of redundant modules with multiple fault occurrences. The case study experiments are carried out with our robot verification platform utilizing the so-called left-hand algorithm and fault injection into a Field Programmable Gate Array (FPGA) implementing the robot controller. This approach is not limited to FPGAs, however, we use an FPGA technology during the evaluation for its wide range of applications and its versatility.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 6th Prague Embedded Systems Workshop

ISBN

978-80-01-06456-6

ISSN

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e-ISSN

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Počet stran výsledku

2

Strana od-do

31-32

Název nakladatele

Faculty of Information Technology, Czech Technical University

Místo vydání

Roztoky u Prahy

Místo konání akce

Roztoky u Prahy

Datum konání akce

28. 6. 2018

Typ akce podle státní příslušnosti

EUR - Evropská akce

Kód UT WoS článku

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