Efficient Implementation of Bi-functional RTL Components - Case Study

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F18%3APU130787" target="_blank" >RIV/00216305:26230/18:PU130787 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1109/NGCAS.2018.8572235" target="_blank" >http://dx.doi.org/10.1109/NGCAS.2018.8572235</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/NGCAS.2018.8572235" target="_blank" >10.1109/NGCAS.2018.8572235</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Efficient Implementation of Bi-functional RTL Components - Case Study

Popis výsledku v původním jazyce

The emergence of highly optimized implementations of many bi-functional gates allows an efficient implementation of components at a higher level of abstraction. In several classes of applications which typically involve RT level oriented design approach, these components can circumvent various issues related to synthesis of multifunctional circuits at the gate level. While the synthesis at the gate level is difficult, at RT level a skilled designer is still able to design a far more complex circuits by himself. If a set of efficient bi-functional RTL components is available, their utilization is expected to improve efficiency of the resulting circuit. In this paper, validity of this assumption is demonstrated through a design of bi-functional adder/subtractor circuit. At the gate level, one-bit full adder/subtractor circuit was created and optimised. This circuit was subsequently utilised for design of multi-bit adder/subtractor which was successfully simulated at the transistor level with MOSFET implementation of bi-functional logic gates. Besides adder/subtractor, an increment/decrement RTL component is also presented.

Název v anglickém jazyce

Efficient Implementation of Bi-functional RTL Components - Case Study

Popis výsledku anglicky

The emergence of highly optimized implementations of many bi-functional gates allows an efficient implementation of components at a higher level of abstraction. In several classes of applications which typically involve RT level oriented design approach, these components can circumvent various issues related to synthesis of multifunctional circuits at the gate level. While the synthesis at the gate level is difficult, at RT level a skilled designer is still able to design a far more complex circuits by himself. If a set of efficient bi-functional RTL components is available, their utilization is expected to improve efficiency of the resulting circuit. In this paper, validity of this assumption is demonstrated through a design of bi-functional adder/subtractor circuit. At the gate level, one-bit full adder/subtractor circuit was created and optimised. This circuit was subsequently utilised for design of multi-bit adder/subtractor which was successfully simulated at the transistor level with MOSFET implementation of bi-functional logic gates. Besides adder/subtractor, an increment/decrement RTL component is also presented.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)<br>S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2018

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2018 New Generation of CAS (NGCAS)

ISBN

978-1-5386-7680-6

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

25-28

Název nakladatele

IEEE Circuits and Systems Society

Místo vydání

Valletta

Místo konání akce

Valletta, Malta

Datum konání akce

20. 11. 2018

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000461061000007