Statistical Model Checking of Approximate Circuits: Challenges and Opportunities

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU135363" target="_blank" >RIV/00216305:26230/20:PU135363 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9116207" target="_blank" >https://ieeexplore.ieee.org/document/9116207</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.23919/DATE48585.2020.9116207" target="_blank" >10.23919/DATE48585.2020.9116207</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Statistical Model Checking of Approximate Circuits: Challenges and Opportunities

Popis výsledku v původním jazyce

Many works have shown that approximate circuits may play an important role in the development of resource-efficient electronic systems. This motivates many researchers to propose new approaches for finding an optimal trade-off between the approximation error and resource savings for predefined applications of approximate circuits. The works and approaches, however, focus mainly on design aspects regarding relaxed functional requirements while neglecting further aspects such as signal and parameter dynamics/stochasticity, relaxed/non-functional equivalence, testing or formal verification. This paper aims to take a step ahead by moving towards the formal verification of time-dependent properties of systems based on approximate circuits. Firstly, it presents our approach to modeling such systems by means of stochastic timed automata whereas our approach goes beyond digital, combinational and/or synchronous circuits and is applicable in the area of sequential, analog and/or asynchronous circuits as well. Secondly, the paper shows the principle and advantage of verifying properties of modeled approximate systems by the statistical model checking technique. Finally, the paper evaluates our approach and outlines future research perspectives.

Název v anglickém jazyce

Statistical Model Checking of Approximate Circuits: Challenges and Opportunities

Popis výsledku anglicky

Many works have shown that approximate circuits may play an important role in the development of resource-efficient electronic systems. This motivates many researchers to propose new approaches for finding an optimal trade-off between the approximation error and resource savings for predefined applications of approximate circuits. The works and approaches, however, focus mainly on design aspects regarding relaxed functional requirements while neglecting further aspects such as signal and parameter dynamics/stochasticity, relaxed/non-functional equivalence, testing or formal verification. This paper aims to take a step ahead by moving towards the formal verification of time-dependent properties of systems based on approximate circuits. Firstly, it presents our approach to modeling such systems by means of stochastic timed automata whereas our approach goes beyond digital, combinational and/or synchronous circuits and is applicable in the area of sequential, analog and/or asynchronous circuits as well. Secondly, the paper shows the principle and advantage of verifying properties of modeled approximate systems by the statistical model checking technique. Finally, the paper evaluates our approach and outlines future research perspectives.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

<a href="/cs/project/LQ1602" target="_blank" >LQ1602: IT4Innovations excellence in science</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition (DATE)

ISBN

978-3-9819263-4-7

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

1574-1577

Název nakladatele

IEEE Computer Society

Místo vydání

Grenoble

Místo konání akce

Grenoble

Datum konání akce

9. 3. 2020

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000610549200286