EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F00216305%3A26230%2F20%3APU138645" target="_blank" >RIV/00216305:26230/20:PU138645 - isvavai.cz</a>

Výsledek na webu

<a href="https://www.fit.vut.cz/research/publication/12104/" target="_blank" >https://www.fit.vut.cz/research/publication/12104/</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1007/s10710-020-09376-3" target="_blank" >10.1007/s10710-020-09376-3</a>

Jazyk výsledku

angličtina

Název v původním jazyce

EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits

Popis výsledku v původním jazyce

Since the early nineties the lack of scalability of fitness evaluation has been the main bottleneck preventing the adoption of evolutionary algorithms for logic circuits synthesis. Recently, various formal approaches such as SAT and BDD solvers have been introduced to this field to overcome this issue. This made it possible to optimise complex circuits consisting of hundreds of inputs and thousands of gates. Unfortunately, we are facing another problem-scalability of representation. The efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing complexity. To overcome this issue, we propose to apply the concept of local resynthesis in this work. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. When applied appropriately, this approach can mitigate the problem of scalability of representation. Two complementary approaches to the extraction of the sub-circuits are presented and evaluated in this work. The evaluation is done on a set of highly optimized complex benchmark problems representing various real-world controllers, logic and arithmetic circuits. The experimental results show that the evolutionary resynthesis provides better results compared to globally operating evolutionary optimization. In more than 85% cases, a substantially higher number of redundant gates was removed while keeping the computational effort at the same level. A huge improvement was achieved especially for the arithmetic circuits. On average, the proposed method was able to remove 25.1% more gates.

Název v anglickém jazyce

EA-based Resynthesis: An Efficient Tool for Optimization of Digital Circuits

Popis výsledku anglicky

Since the early nineties the lack of scalability of fitness evaluation has been the main bottleneck preventing the adoption of evolutionary algorithms for logic circuits synthesis. Recently, various formal approaches such as SAT and BDD solvers have been introduced to this field to overcome this issue. This made it possible to optimise complex circuits consisting of hundreds of inputs and thousands of gates. Unfortunately, we are facing another problem-scalability of representation. The efficiency of the evolutionary optimization applied at the global level deteriorates with the increasing complexity. To overcome this issue, we propose to apply the concept of local resynthesis in this work. Local resynthesis is an iterative process based on the extraction of smaller sub-circuits from a complex circuit that are optimized locally and implanted back to the original circuit. When applied appropriately, this approach can mitigate the problem of scalability of representation. Two complementary approaches to the extraction of the sub-circuits are presented and evaluated in this work. The evaluation is done on a set of highly optimized complex benchmark problems representing various real-world controllers, logic and arithmetic circuits. The experimental results show that the evolutionary resynthesis provides better results compared to globally operating evolutionary optimization. In more than 85% cases, a substantially higher number of redundant gates was removed while keeping the computational effort at the same level. A huge improvement was achieved especially for the arithmetic circuits. On average, the proposed method was able to remove 25.1% more gates.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Genetic Programming and Evolvable Machines

ISSN

1389-2576

e-ISSN

1573-7632

Svazek periodika

21

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

33

Strana od-do

287-319

Kód UT WoS článku

000510271200002

EID výsledku v databázi Scopus

2-s2.0-85078849825