PolarFire FPGA Radiation Endurance Testing Platform

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F49777513%3A23220%2F24%3A43973922" target="_blank" >RIV/49777513:23220/24:43973922 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/10819095" target="_blank" >https://ieeexplore.ieee.org/document/10819095</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/TELFOR63250.2024.10819095" target="_blank" >10.1109/TELFOR63250.2024.10819095</a>

Jazyk výsledku

angličtina

Název v původním jazyce

PolarFire FPGA Radiation Endurance Testing Platform

Popis výsledku v původním jazyce

Radiation endurance testing is crucial for electronic components used in environments with high levels of ionizing radiation, such as aerospace, military, and certain medical applications. This paper presents a testing platform designed to evaluate the radiation tolerance of FPGAs, particularly focusing on a flash-based FPGA from Microchip’s PolarFire family. The system architecture integrates a device under test (DUT) and a tester FPGA on the same board, with supporting hardware to monitor and record radiation-induced errors. A simplified power topology was proposed to reduce complexity without compromising stability. Additionally, the platform supports high-speed data acquisition and real-time error analysis, offering a reliable solution for FPGA radiation testing.

Název v anglickém jazyce

PolarFire FPGA Radiation Endurance Testing Platform

Popis výsledku anglicky

Radiation endurance testing is crucial for electronic components used in environments with high levels of ionizing radiation, such as aerospace, military, and certain medical applications. This paper presents a testing platform designed to evaluate the radiation tolerance of FPGAs, particularly focusing on a flash-based FPGA from Microchip’s PolarFire family. The system architecture integrates a device under test (DUT) and a tester FPGA on the same board, with supporting hardware to monitor and record radiation-induced errors. A simplified power topology was proposed to reduce complexity without compromising stability. Additionally, the platform supports high-speed data acquisition and real-time error analysis, offering a reliable solution for FPGA radiation testing.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2024

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

2024 32nd Telecommunications Forum (TELFOR) : Proceedings

ISBN

979-8-3503-9106-0

ISSN

2994-581X

e-ISSN

2994-5828

Počet stran výsledku

4

Strana od-do

—

Název nakladatele

IEEE

Místo vydání

Piscataway

Místo konání akce

Belgrade, Serbia

Datum konání akce

26. 11. 2024

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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