Theory and Original Design of Resistive-Inductive Network High-Pass Negative Group Delay Integrated Circuit in 130-nm CMOS Technology

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F61989100%3A27240%2F22%3A10250105" target="_blank" >RIV/61989100:27240/22:10250105 - isvavai.cz</a>

Výsledek na webu

<a href="https://ieeexplore.ieee.org/document/9729790" target="_blank" >https://ieeexplore.ieee.org/document/9729790</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/ACCESS.2022.3157381" target="_blank" >10.1109/ACCESS.2022.3157381</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Theory and Original Design of Resistive-Inductive Network High-Pass Negative Group Delay Integrated Circuit in 130-nm CMOS Technology

Popis výsledku v původním jazyce

This paper develops an original design method of high-pass (HP) negative group delay (NGD) integrated circuit (IC). The considered HP-NGD IC is based on a passive topology which is essentially composed of resistor-inductor (RL) network. The paper presents the first time that an unfamiliar HP-topology is designed in miniaturized circuit implemented in 130-nm CMOS technology. The theory of unfamiliar HP-NGD topology based on the voltage transfer function (VTF) analysis is elaborated. The design equations with synthesis formulas of the resistor and inductor are established. The HP-NGD IC CMOS design methodology is introduced. The feasibility of the miniature NGD IC implementation is approved by design rule check (DRC) and layout versus schematic (LVS) approaches. The HP-NGD passive IC is designed in 130-nm CMOS technology. The HP-NGD topology is constituted by RL-network based on CMOS high Ohmic unsalicided N + poly resistor and symmetrical high current spiral inductor. Then, the schematic and layout simulations are presented. The validity of the 130-nm CMOS HP-NGD design is verified by the investigation of 225 mu m x 215 mu m chip two different miniature circuit proofs-of-concept (POC). The HP-NGD behavior is validated by comparison between the calculated, and schematic and post-layout simulations of the HP-NGD POCs carried out by a commercial tool. As expected, the group delay and VTF magnitude diagrams are in very good correlation. HP-NGD optimal value, NGD cut-off frequency and attenuation, of about (-31 ps, 141 MHz, -3 dB) and (-47 ps, 204 MHz, -5 dB) are obtained from the miniature POCs.

Název v anglickém jazyce

Theory and Original Design of Resistive-Inductive Network High-Pass Negative Group Delay Integrated Circuit in 130-nm CMOS Technology

Popis výsledku anglicky

This paper develops an original design method of high-pass (HP) negative group delay (NGD) integrated circuit (IC). The considered HP-NGD IC is based on a passive topology which is essentially composed of resistor-inductor (RL) network. The paper presents the first time that an unfamiliar HP-topology is designed in miniaturized circuit implemented in 130-nm CMOS technology. The theory of unfamiliar HP-NGD topology based on the voltage transfer function (VTF) analysis is elaborated. The design equations with synthesis formulas of the resistor and inductor are established. The HP-NGD IC CMOS design methodology is introduced. The feasibility of the miniature NGD IC implementation is approved by design rule check (DRC) and layout versus schematic (LVS) approaches. The HP-NGD passive IC is designed in 130-nm CMOS technology. The HP-NGD topology is constituted by RL-network based on CMOS high Ohmic unsalicided N + poly resistor and symmetrical high current spiral inductor. Then, the schematic and layout simulations are presented. The validity of the 130-nm CMOS HP-NGD design is verified by the investigation of 225 mu m x 215 mu m chip two different miniature circuit proofs-of-concept (POC). The HP-NGD behavior is validated by comparison between the calculated, and schematic and post-layout simulations of the HP-NGD POCs carried out by a commercial tool. As expected, the group delay and VTF magnitude diagrams are in very good correlation. HP-NGD optimal value, NGD cut-off frequency and attenuation, of about (-31 ps, 141 MHz, -3 dB) and (-47 ps, 204 MHz, -5 dB) are obtained from the miniature POCs.

Druh

J_imp - Článek v periodiku v databázi Web of Science

CEP obor

—

OECD FORD obor

20200 - Electrical engineering, Electronic engineering, Information engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2022

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

IEEE ACCESS

ISSN

2169-3536

e-ISSN

2169-3536

Svazek periodika

10

Číslo periodika v rámci svazku

2022

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

15

Strana od-do

27147-27161

Kód UT WoS článku

000769966700001

EID výsledku v databázi Scopus

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