Pipelined ALU for effective external memory access in FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F63839172%3A_____%2F20%3A10133299" target="_blank" >RIV/63839172:_____/20:10133299 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21240/20:00342829 RIV/00216305:26230/20:PU139367

Výsledek na webu

<a href="http://dx.doi.org/10.1109/DSD51259.2020.00026" target="_blank" >http://dx.doi.org/10.1109/DSD51259.2020.00026</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1109/DSD51259.2020.00026" target="_blank" >10.1109/DSD51259.2020.00026</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Pipelined ALU for effective external memory access in FPGA

Popis výsledku v původním jazyce

The external memories in digital design are closely related to high response time. The most common approach to mitigate latency is adding a caching mechanism into the memory subsystem. This solution might be sufficient in CPU architecture, where we can reschedule operations when a cache miss occurs. However, the FPGA architectures are usually accelerators with simple functionality, where it is not possible to postpone work. The cache miss often leads to whole pipeline stall or even to data loss. The architecture we present in this paper reduces this problem by aggregating arithmetic operations into the memory subsystem itself. Our architecture reaches a speed of 200 Mp/s (operations carried out). It is designed to be used in systems with link speeds of 100 Gb/s. It outperforms other implementations by a factor of at least 3. The additional benefit of our architecture is reducing the number of memory transactions by a factor of two on real-world datasets.

Název v anglickém jazyce

Pipelined ALU for effective external memory access in FPGA

Popis výsledku anglicky

The external memories in digital design are closely related to high response time. The most common approach to mitigate latency is adding a caching mechanism into the memory subsystem. This solution might be sufficient in CPU architecture, where we can reschedule operations when a cache miss occurs. However, the FPGA architectures are usually accelerators with simple functionality, where it is not possible to postpone work. The cache miss often leads to whole pipeline stall or even to data loss. The architecture we present in this paper reduces this problem by aggregating arithmetic operations into the memory subsystem itself. Our architecture reaches a speed of 200 Mp/s (operations carried out). It is designed to be used in systems with link speeds of 100 Gb/s. It outperforms other implementations by a factor of at least 3. The additional benefit of our architecture is reducing the number of memory transactions by a factor of two on real-world datasets.

Druh

D - Stať ve sborníku

CEP obor

—

OECD FORD obor

20206 - Computer hardware and architecture

Projekt

<a href="/cs/project/EF16_013%2F0001797" target="_blank" >EF16_013/0001797: E-infrastruktura CESNET - modernizace</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2020

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 23rd Euromicro Conference on Digital Systems Design

ISBN

978-1-72819-535-3

ISSN

—

e-ISSN

—

Počet stran výsledku

4

Strana od-do

97-100

Název nakladatele

IEEE

Místo vydání

Los Alamitos, California

Místo konání akce

Kranj, Slovinsko

Datum konání akce

26. 8. 2020

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000630443300015