Comuputation of Long Time Cross Ambiguity function using reconfigurable HW

Kód výsledku v IS VaVaI

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Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Comuputation of Long Time Cross Ambiguity function using reconfigurable HW

Popis výsledku v původním jazyce

In modern radio location systems based on passive coherent location (PCL), one of the key problems is an efficient and accurate computation of the cross ambiguity function (CAF). This function is related to the direct signal and signals reflected from localized targets. CAF represent power spectral density distribution of the cross-correlation between direct and reflected signals. In this paper we present an attempt to implement (numerically effective and sufficiently accurate) the CAF computation accelerator on FPGA. The results show that this accelerator could be used to compute CAF in real-time in the future PCL systems. The presented design has been implemented in PC accelerator cards based both on Xilinx Virtex IV and Altera Stratix II devices. The presented contribution gives overall information about the algorithms, accelerator architecture design and achieved performance. The possibilities of the future enhancements are discussed.

Název v anglickém jazyce

Comuputation of Long Time Cross Ambiguity function using reconfigurable HW

Popis výsledku anglicky

In modern radio location systems based on passive coherent location (PCL), one of the key problems is an efficient and accurate computation of the cross ambiguity function (CAF). This function is related to the direct signal and signals reflected from localized targets. CAF represent power spectral density distribution of the cross-correlation between direct and reflected signals. In this paper we present an attempt to implement (numerically effective and sufficiently accurate) the CAF computation accelerator on FPGA. The results show that this accelerator could be used to compute CAF in real-time in the future PCL systems. The presented design has been implemented in PC accelerator cards based both on Xilinx Virtex IV and Altera Stratix II devices. The presented contribution gives overall information about the algorithms, accelerator architecture design and achieved performance. The possibilities of the future enhancements are discussed.

Druh

D - Stať ve sborníku

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

Výsledek vznikl pri realizaci vícero projektů. Více informací v záložce Projekty.

Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2006

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 6th IEEE International Symposium on Signal Processing and Information Technology

ISBN

978-0-7803-9753-8

ISSN

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e-ISSN

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Počet stran výsledku

5

Strana od-do

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Název nakladatele

IEEE

Místo vydání

Vancouver

Místo konání akce

Vancouver

Datum konání akce

27. 8. 2006

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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