Parity Codes Used for On-line Testing in FPGA

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F05%3A03117292" target="_blank" >RIV/68407700:21230/05:03117292 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Parity Codes Used for On-line Testing in FPGA

Popis výsledku v původním jazyce

This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes.The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented.

Název v anglickém jazyce

Parity Codes Used for On-line Testing in FPGA

Popis výsledku anglicky

This article deals with the on-line error detection in digital circuits implemented in FPGAs. The error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of errors. Hence a safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. The combinational circuits bench-marks have been used in this work in order to compute a quality of the proposed codes.The benchmarks description is based on equations and tables. All of our experiments results are ob-tained by XILINX FPGA implementation EDA tools. The possible TSC structure consisting sev-eral TSC blocks is presented.

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2005

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Acta Polytechnica

ISSN

1210-2709

e-ISSN

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Svazek periodika

45

Číslo periodika v rámci svazku

6

Stát vydavatele periodika

CZ - Česká republika

Počet stran výsledku

7

Strana od-do

53-59

Kód UT WoS článku

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EID výsledku v databázi Scopus

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