Low Complex Interoperable GNSS Signal Processor and its Performance

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F10%3A00169728" target="_blank" >RIV/68407700:21230/10:00169728 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Low Complex Interoperable GNSS Signal Processor and its Performance

Popis výsledku v původním jazyce

The recent development of the GNSS systems and international cooperation resulted in important technical problems of the GNSS systems which are an interoperability and compatibility. In the interoperable receivers the most expensive parts - front ends -can be shared for signals reception of different systems. The unification of the signal processor is also possible with some small performance deterioration but the hardware complexity reduction is considerable. The paper analyses applicability of a classical E-L correlator for processing of various GNSS signals and compare its performance with optimal method. The low complex interoperable processor of software receiver based on a FPGA for the GPS, Galileo and GLONASS systems is proposed. The results oftesting on the Galileo E1 and E5 signals are presented. The last part of the paper proposes architecture of a low cost multi system GNSS receiver based on mass market components.

Název v anglickém jazyce

Low Complex Interoperable GNSS Signal Processor and its Performance

Popis výsledku anglicky

The recent development of the GNSS systems and international cooperation resulted in important technical problems of the GNSS systems which are an interoperability and compatibility. In the interoperable receivers the most expensive parts - front ends -can be shared for signals reception of different systems. The unification of the signal processor is also possible with some small performance deterioration but the hardware complexity reduction is considerable. The paper analyses applicability of a classical E-L correlator for processing of various GNSS signals and compare its performance with optimal method. The low complex interoperable processor of software receiver based on a FPGA for the GPS, Galileo and GLONASS systems is proposed. The results oftesting on the Galileo E1 and E5 signals are presented. The last part of the paper proposes architecture of a low cost multi system GNSS receiver based on mass market components.

Druh

D - Stať ve sborníku

CEP obor

JA - Elektronika a optoelektronika, elektrotechnika

OECD FORD obor

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Projekt

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Návaznosti

Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění

2010

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 2010 IEEE/ION Position, Location and Navigation Symposium

ISBN

978-1-4244-5037-4

ISSN

2153-358X

e-ISSN

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Počet stran výsledku

5

Strana od-do

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Název nakladatele

IEEE

Místo vydání

Piscataway

Místo konání akce

Indian Wells, CA

Datum konání akce

4. 5. 2010

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

000287515800067