A Real-Time MultiChannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F15%3A00224133" target="_blank" >RIV/68407700:21230/15:00224133 - isvavai.cz</a>

Výsledek na webu

<a href="http://dx.doi.org/10.1145/2661635" target="_blank" >http://dx.doi.org/10.1145/2661635</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.1145/2661635" target="_blank" >10.1145/2661635</a>

Jazyk výsledku

angličtina

Název v původním jazyce

A Real-Time MultiChannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Popis výsledku v původním jazyce

Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in multiprocessor real-time systems depends on mapping of the memory clients to the memory channels according to their requirements on latency, bandwidth, communication, and memory capacity. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multichannel memories in real-time systems. As a first work toward this direction, we present two main contributions in this article: (1) a configurable real-time multichannel memory controller architecture with a novel method for logical-to-physical address translation and (2) two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping

Název v anglickém jazyce

A Real-Time MultiChannel Memory Controller and Optimal Mapping of Memory Clients to Memory Channels

Popis výsledku anglicky

Ever-increasing demands for main memory bandwidth and memory speed/power tradeoff led to the introduction of memories with multiple memory channels, such as Wide IO DRAM. Efficient utilization of a multichannel memory as a shared resource in multiprocessor real-time systems depends on mapping of the memory clients to the memory channels according to their requirements on latency, bandwidth, communication, and memory capacity. However, there is currently no real-time memory controller for multichannel memories, and there is no methodology to optimally configure multichannel memories in real-time systems. As a first work toward this direction, we present two main contributions in this article: (1) a configurable real-time multichannel memory controller architecture with a novel method for logical-to-physical address translation and (2) two design-time methods to map memory clients to the memory channels, one an optimal algorithm based on an integer programming formulation of the mapping

Druh

J_x - Nezařazeno - Článek v odborném periodiku (Jimp, Jsc a Jost)

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

—

Projekt

<a href="/cs/project/EE2.3.30.0034" target="_blank" >EE2.3.30.0034: Podpora zkvalitnění týmů výzkumu a vývoje a rozvoj intersektorální mobility na ČVUT v Praze</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2015

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

ACM Transactions on Embedded Computing Systems

ISSN

1539-9087

e-ISSN

—

Svazek periodika

14

Číslo periodika v rámci svazku

2

Stát vydavatele periodika

US - Spojené státy americké

Počet stran výsledku

25

Strana od-do

1-25

Kód UT WoS článku

000352224800006

EID výsledku v databázi Scopus

2-s2.0-84923668300