Methods and Hardware achitecture for Multi-constellation GNSS signal acqusition unit in frequency domain

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F17%3A00312222" target="_blank" >RIV/68407700:21230/17:00312222 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21240/17:00312222

Výsledek na webu

<a href="http://enc2017.eu/site/downloads/" target="_blank" >http://enc2017.eu/site/downloads/</a>

DOI - Digital Object Identifier

—

Jazyk výsledku

angličtina

Název v původním jazyce

Methods and Hardware achitecture for Multi-constellation GNSS signal acqusition unit in frequency domain

Popis výsledku v původním jazyce

The objective of this contribution is a design of universal GNSS acquisition unit for an FPGA-based HW receiver, which is able of direct acquisition of usual civil signals (GPS C/A, BeiDou B1, IRNSS L5/S-band, and GLONASS L1OF). Due to high complexity of calculation and requirements for latency, processing in frequency domain with parallel search in code is adopted. Optimal processing methods even for the long codes of Galileo E1 or future GPS L1C signals are analyzed. For each block of the acquisition unit, a method is selected with respect to implementation on the target System on Chip (SoC) Xilinx ZYNQ platform. The unit is intended as a HW acquisition accelerator with a minimal SW handling requirements for the developed receiver.

Název v anglickém jazyce

Methods and Hardware achitecture for Multi-constellation GNSS signal acqusition unit in frequency domain

Popis výsledku anglicky

The objective of this contribution is a design of universal GNSS acquisition unit for an FPGA-based HW receiver, which is able of direct acquisition of usual civil signals (GPS C/A, BeiDou B1, IRNSS L5/S-band, and GLONASS L1OF). Due to high complexity of calculation and requirements for latency, processing in frequency domain with parallel search in code is adopted. Optimal processing methods even for the long codes of Galileo E1 or future GPS L1C signals are analyzed. For each block of the acquisition unit, a method is selected with respect to implementation on the target System on Chip (SoC) Xilinx ZYNQ platform. The unit is intended as a HW acquisition accelerator with a minimal SW handling requirements for the developed receiver.

Druh

O - Ostatní výsledky

CEP obor

—

OECD FORD obor

20202 - Communication engineering and systems

Projekt

<a href="/cs/project/TE01020186" target="_blank" >TE01020186: Centrum integrovaných družicových a pozemských navigačních technologií</a><br>

Návaznosti

P - Projekt vyzkumu a vyvoje financovany z verejnych zdroju (s odkazem do CEP)

Rok uplatnění

2017

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů