Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F19%3A00333838" target="_blank" >RIV/68407700:21230/19:00333838 - isvavai.cz</a>

Výsledek na webu

<a href="https://doi.org/10.15598/aeee.v17i3.3061" target="_blank" >https://doi.org/10.15598/aeee.v17i3.3061</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.15598/aeee.v17i3.3061" target="_blank" >10.15598/aeee.v17i3.3061</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

Popis výsledku v původním jazyce

This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, such as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump Design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc., are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were found based on the time response characteristics of the pump sub-block. The goals include both maximize the voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc.

Název v anglickém jazyce

Cross-Coupled Charge Pump Synthesis Based on Full Transistor-Level

Popis výsledku anglicky

This paper presents utility for the design of the cross-coupled charge pump, which is used for supplying peripherals with low current consumption on the chip, such as the EEPROM or FLASH memories. The article summarizes the knowledge in the field of the theoretical and practical analysis of the cross-coupled charge pump Design relationships and their connection with the pump parameters, as the threshold voltage, power supply voltage, clock signal frequency, etc., are applicated in the design algorithm. Optimal MOSFETs sizes (W, L) were found based on the time response characteristics of the pump sub-block. The goals include both maximize the voltage increase in the active interval of the clock signal and minimizing of the pump losses, as the switch reverse current, inverter cross current, etc.

Druh

J_SC - Článek v periodiku v databázi SCOPUS

CEP obor

—

OECD FORD obor

20201 - Electrical and electronic engineering

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2019

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název periodika

Advances in Electrical and Electronic Engineering

ISSN

1336-1376

e-ISSN

1804-3119

Svazek periodika

17

Číslo periodika v rámci svazku

3

Stát vydavatele periodika

CZ - Česká republika

Počet stran výsledku

9

Strana od-do

285-293

Kód UT WoS článku

000488257400008

EID výsledku v databázi Scopus

2-s2.0-85073535577