Automatic Placer for Analog Circuits Using Integer Linear Programming Warm Started by Graph Drawing

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21230%2F23%3A00364869" target="_blank" >RIV/68407700:21230/23:00364869 - isvavai.cz</a>

Nalezeny alternativní kódy

RIV/68407700:21730/23:00364869

Výsledek na webu

<a href="https://doi.org/10.5220/0011789300003396" target="_blank" >https://doi.org/10.5220/0011789300003396</a>

DOI - Digital Object Identifier

<a href="http://dx.doi.org/10.5220/0011789300003396" target="_blank" >10.5220/0011789300003396</a>

Jazyk výsledku

angličtina

Název v původním jazyce

Automatic Placer for Analog Circuits Using Integer Linear Programming Warm Started by Graph Drawing

Popis výsledku v původním jazyce

Due to its diversity, the physical design of the Analog and Mixed-Signal Integrated Circuits is not as automated as the physical design of digital Integrated Circuits. The placement process is one of the critical steps of the physical design, and automating it would significantly shorten the design time. We formulate the placement process using an Integer Linear Programming approach, with features to support a specific semiconductor technology. We include an enumeration of possible variants of the circuit’s topological structures, which are afterward considered during optimization. We use the Gurobi solver to minimize both the approximate wire length and the placement area. The results were evaluated by layout design experts and compared with manual designs. We also utilize a graph drawing-based method to generate an initial feasible solution to warm start the Integer Linear Programming solver, which noticeably improves the performance and shortens the computation time (5x to 15x), a nd makes the approach applicable even for larger problem instances containing 100 independent elements. Experiments performed on real-life industrial problem instances show that our graph drawing-enhanced approach can produce high-quality placement in a much shorter time than the designers need.

Název v anglickém jazyce

Automatic Placer for Analog Circuits Using Integer Linear Programming Warm Started by Graph Drawing

Popis výsledku anglicky

Due to its diversity, the physical design of the Analog and Mixed-Signal Integrated Circuits is not as automated as the physical design of digital Integrated Circuits. The placement process is one of the critical steps of the physical design, and automating it would significantly shorten the design time. We formulate the placement process using an Integer Linear Programming approach, with features to support a specific semiconductor technology. We include an enumeration of possible variants of the circuit’s topological structures, which are afterward considered during optimization. We use the Gurobi solver to minimize both the approximate wire length and the placement area. The results were evaluated by layout design experts and compared with manual designs. We also utilize a graph drawing-based method to generate an initial feasible solution to warm start the Integer Linear Programming solver, which noticeably improves the performance and shortens the computation time (5x to 15x), a nd makes the approach applicable even for larger problem instances containing 100 independent elements. Experiments performed on real-life industrial problem instances show that our graph drawing-enhanced approach can produce high-quality placement in a much shorter time than the designers need.

Druh

D - Stať ve sborníku

CEP obor

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OECD FORD obor

10201 - Computer sciences, information science, bioinformathics (hardware development to be 2.2, social aspect to be 5.8)

Projekt

—

Návaznosti

S - Specificky vyzkum na vysokych skolach

Rok uplatnění

2023

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

Název statě ve sborníku

Proceedings of the 12th International Conference on Operations Research and Enterprise Systems

ISBN

978-989-758-627-9

ISSN

2184-4372

e-ISSN

2184-4372

Počet stran výsledku

11

Strana od-do

106-116

Název nakladatele

Science and Technology Publications, Lda

Místo vydání

Setúbal

Místo konání akce

Lisabon

Datum konání akce

19. 2. 2023

Typ akce podle státní příslušnosti

WRD - Celosvětová akce

Kód UT WoS článku

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