Design of scalable structures with defined dependability for system on chip

Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00167410" target="_blank" >RIV/68407700:21240/10:00167410 - isvavai.cz</a>
Nalezeny alternativní kódy
RIV/68407700:21230/10:00166068
Výsledek na webu
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DOI - Digital Object Identifier
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Jazyk výsledku
angličtina
Název v původním jazyce
Design of scalable structures with defined dependability for system on chip
Popis výsledku v původním jazyce
This paper summarizes previous work, which observed design finite state machines of MOORE type with self-checking architecture. My concept is proved on a practical problem, which is implementing the railway station system in the FPGA. The safety device for any configuration of railway station can be built from five basic blocks. Each block is based on a finite state machine of MOORE type. My methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.
Název v anglickém jazyce
Design of scalable structures with defined dependability for system on chip
Popis výsledku anglicky
This paper summarizes previous work, which observed design finite state machines of MOORE type with self-checking architecture. My concept is proved on a practical problem, which is implementing the railway station system in the FPGA. The safety device for any configuration of railway station can be built from five basic blocks. Each block is based on a finite state machine of MOORE type. My methodology is intended for final implementation in FPGA and hence SEU faults occurring in the system is assumed.

Projekt
<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>
Návaznosti
Z - Vyzkumny zamer (s odkazem do CEZ)

Rok uplatnění
2010
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

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