Time-Area Efficient HW Architectures for Cryptography and Cryptanalysis

Kód výsledku v IS VaVaI

<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00167731" target="_blank" >RIV/68407700:21240/10:00167731 - isvavai.cz</a>

Výsledek na webu

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DOI - Digital Object Identifier

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Jazyk výsledku

angličtina

Název v původním jazyce

Time-Area Efficient HW Architectures for Cryptography and Cryptanalysis

Popis výsledku v původním jazyce

The first part of the book focuses on hardware architectures operating over elements of GF(2^m) in normal basis representation. Such architectures are applicable e.g. in Elliptic Curve Cryptography. Four new architectures of digit-serial normal basis multipliers are presented. Based on these architectures, a novel structure of a normal basis arithmetic unit is proposed. As the unit is both small and scalable, the design constrains can be met optimally. The second part of the thesis focuses on the cryptanalysis of the A5/1 cipher used in GSM communications. Hardware architectures of two attacks against the A5/1 cipher are presented. The attacks have been implemented using an existing low-cost special-purpose hardware device: COPACOBANA. The attacks aredesigned to utilize both the properties of the cipher and the features of underlying reconfigurable hardware. Presented design approaches can be reused when designing attacks against similar ciphers.

Název v anglickém jazyce

Time-Area Efficient HW Architectures for Cryptography and Cryptanalysis

Popis výsledku anglicky

The first part of the book focuses on hardware architectures operating over elements of GF(2^m) in normal basis representation. Such architectures are applicable e.g. in Elliptic Curve Cryptography. Four new architectures of digit-serial normal basis multipliers are presented. Based on these architectures, a novel structure of a normal basis arithmetic unit is proposed. As the unit is both small and scalable, the design constrains can be met optimally. The second part of the thesis focuses on the cryptanalysis of the A5/1 cipher used in GSM communications. Hardware architectures of two attacks against the A5/1 cipher are presented. The attacks have been implemented using an existing low-cost special-purpose hardware device: COPACOBANA. The attacks aredesigned to utilize both the properties of the cipher and the features of underlying reconfigurable hardware. Presented design approaches can be reused when designing attacks against similar ciphers.

Druh

B - Odborná kniha

CEP obor

JC - Počítačový hardware a software

OECD FORD obor

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Projekt

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Návaznosti

N - Vyzkumna aktivita podporovana z neverejnych zdroju

Rok uplatnění

2010

Kód důvěrnosti údajů

S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů

ISBN

978-3-89966-351-8

Počet stran knihy

194

Název nakladatele

Europäischer Universitätsverlag

Místo vydání

Bochum

Kód UT WoS knihy

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