It Is Better to Run Iterative Resynthesis on Parts of the Circuit
Identifikátory výsledku
Kód výsledku v IS VaVaI
<a href="https://www.isvavai.cz/riv?ss=detail&h=RIV%2F68407700%3A21240%2F10%3A00168665" target="_blank" >RIV/68407700:21240/10:00168665 - isvavai.cz</a>
Výsledek na webu
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DOI - Digital Object Identifier
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Alternativní jazyky
Jazyk výsledku
angličtina
Název v původním jazyce
It Is Better to Run Iterative Resynthesis on Parts of the Circuit
Popis výsledku v původním jazyce
In this paper we investigate iterative logic synthesis processes. A well known academic logic synthesis tool ABC incorporates many synthesis algorithms and scripts which may be run iteratively to possibly improve the result. When iterating the synthesisprocess, the whole network is considered. We propose an alternative approach to iterative synthesis - only properly selected parts of the circuit are submitted to resynthesis, which is done iteratively. We show that a significant improvement in the result quality may be achieved. This observation is rather surprising and witnesses probably a lack of efficiency of the ABC resynthesis control. The observations are documented by numerous experiments on ISCAS and IWLS'93 benchmark circuits
Název v anglickém jazyce
It Is Better to Run Iterative Resynthesis on Parts of the Circuit
Popis výsledku anglicky
In this paper we investigate iterative logic synthesis processes. A well known academic logic synthesis tool ABC incorporates many synthesis algorithms and scripts which may be run iteratively to possibly improve the result. When iterating the synthesisprocess, the whole network is considered. We propose an alternative approach to iterative synthesis - only properly selected parts of the circuit are submitted to resynthesis, which is done iteratively. We show that a significant improvement in the result quality may be achieved. This observation is rather surprising and witnesses probably a lack of efficiency of the ABC resynthesis control. The observations are documented by numerous experiments on ISCAS and IWLS'93 benchmark circuits
Klasifikace
Druh
O - Ostatní výsledky
CEP obor
JC - Počítačový hardware a software
OECD FORD obor
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Návaznosti výsledku
Projekt
<a href="/cs/project/GA102%2F09%2F1668" target="_blank" >GA102/09/1668: Zvyšování spolehlivosti a provozuschopnosti v obvodech SoC</a><br>
Návaznosti
Z - Vyzkumny zamer (s odkazem do CEZ)
Ostatní
Rok uplatnění
2010
Kód důvěrnosti údajů
S - Úplné a pravdivé údaje o projektu nepodléhají ochraně podle zvláštních právních předpisů